IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 25 / 744

Notes
PES32NT24xG2 User Manual xv January 30, 2013
List of Figures
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Figure 1.1 PES32NT24xG2 Block Diagram ........................................................................................1-3
Figure 1.2 Logical Representation of a Port with PCI-to-PCI bridge, NT, and DMA Functions ..........1-5
Figure 1.3 Transparent PCI Express Switch .......................................................................................1-6
Figure 1.4 Partitionable PCI Express Switch ......................................................................................1-7
Figure 1.5 Non-Transparent Bridge ....................................................................................................1-8
Figure 1.6 Generalized Multi-Port Non-Transparent Interconnect ......................................................1-9
Figure 1.7 Architectural Approaches for Integrating Non-Transparency into a PCI Express Switch .1-10
Figure 1.8 Non-Transparent Switch with Non-Transparency Between Partitions .............................1-11
Figure 1.9 Non-Transparent Switch with Non-Transparent Ports .....................................................1-11
Figure 1.10 Non-Transparent Switch with Non-Transparent Ports .....................................................1-12
Figure 1.11 Non-Transparent Switch with Non-Transparent Ports .....................................................1-12
Figure 1.12 Switch Partition with DMA function ..................................................................................1-13
Figure 1.13 Two Switch Partitions Interconnected by an NTB, with DMA in One Partition .................1-14
Figure 1.14 Two Switch Partitions Interconnected by an NTB, with DMA in Both Partitions ..............1-15
Figure 1.15 Non-Transparent Switch Failover Usage .........................................................................1-16
Figure 1.16 Example of Switch Event Mechanism ..............................................................................1-17
Figure 1.17 Example of Transparent Multicast ...................................................................................1-18
Figure 1.18 Example of Non Transparent Multicast ............................................................................1-18
Figure 2.1 Logical Representation of PES32NT24AG2 Clocking Architecture ...................................2-2
Figure 2.2 Logical Representation of PES32NT24BG2 Clocking Architecture ...................................2-2
Figure 2.3 Clocking Connection for a Port in Global Clocked Mode, with a Common Clocked
Configuration ......................................................................................................................2-3
Figure 2.4 Clocking Connection for a Port in Global Clocked Mode, Non-Common Clocked
Configuration ......................................................................................................................2-4
Figure 2.5 Clocking Connection for a Port in Local Port Clocked Mode, in a Common Clocked
Configuration ......................................................................................................................2-5
Figure 2.6 Clocking Connection for a Port in Local Port Clocked Mode, in a Non-Common
Clocked Configuration ........................................................................................................2-5
Figure 3.1 Switch Fundamental Reset with Serial EEPROM Initialization ..........................................3-3
Figure 3.2 Fundamental Reset Using RSTHALT to Keep Device in Quasi-Reset State .....................3-4
Figure 4.1 High Level Diagram of Switch Core ...................................................................................4-2
Figure 4.2 Architectural Model of Arbitration .......................................................................................4-7
Figure 4.3 PCI Express Switch Static Rate Mismatch .......................................................................4-12
Figure 4.4 PCI Express Switch Static Rate Mismatch .......................................................................4-13
Figure 4.5 Request Metering Counter Decrement Operation ............................................................4-14
Figure 4.6 Non-Posted Read Request Completion Size Estimate Computation ...............................4-15
Figure 4.7 Internal Error Logic in Each PES32NT24xG2 Port ..........................................................4-17
Figure 4.8 Reporting of Port AER Errors as Internal Errors ..............................................................4-21
Figure 5.1 Allowable Partition State Transitions .................................................................................5-4
Figure 5.2 Logical Representation of a Port with PCI-to-PCI bridge, NT, and DMA Functions ..........5-6
Figure 6.1 Failover Policy vs. Failover Reconfiguration ......................................................................6-1
Figure 7.1 Lane Reversal for Highest Achievable Link Width of x2 ....................................................7-2
Figure 7.2 Lane Reversal for Highest Achievable Link Width of x4 ....................................................7-3
Figure 7.3 Lane Reversal for Highest Achievable Link Width of x8 ....................................................7-4
Figure 7.4 PES32NT24xG2 ASPM Link State Transitions ................................................................7-10
Figure 8.1 Relationship Between Coarse and Fine De-emphasis Controls ......................................8-10
Figure 8.2 Effect of Fine de-emphasis Control at Gen 2 with -6.0 dB Nominal de-emphasis ...........8-11
Figure 9.1 PES32NT24xG2 Power Management State Transition Diagram .......................................9-2
Figure 10.1 Logical Representation of INTx Aggregation ...................................................................10-5