IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 143 / 744

IDT Link Operation
PES32NT24xG2 User Manual 7 - 15 January 30, 2013
Notes
A port configured in downstream switch port mode initiates exit from L1 when either of the conditions
listed below is met:
– The port has a TLP scheduled for transmission on the link.
– The upstream port in the switch partition has initiated exit from L1. The latency between the
upstream port’s initiated exit from L1 and the downstream switch port’s initiated exit from L1 must
not exceed 1 µ s.
A port configured in NT function mode or NT with DMA function mode initiates exit from L1 when the
condition listed below is met:
– The port has a TLP scheduled for transmission on the link.
Finally, a port configured in upstream switch port with NT function mode or upstream switch port with NT
and DMA function mode will enter L1 when either of the conditions listed below is met:
– The port has a TLP scheduled for transmission on the link.
– A downstream switch port in the switch partition associated with the PCI-to-PCI bridge function
has initiated exit from L1. The latency between the downstream switch port’s initiated exit from L1
and the upstream port’s initiated exit from L1 must not exceed 1 µ s.
L1 ASPM Entry Rejection Timer
When L1 is enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, the
PES32NT24xG2 downstream switch ports respond to link partner requests to enter the L1 ASPM state.
In order to enter the L1 ASPM link state, a downstream device (e.g., endpoint) sends continuous
PM_Active_State_Request_L1 DLLPs to its link partner (e.g., a downstream switch port). This process
continues until the downstream device receives an acceptance or rejection from its link partner.
A PES32NT24xG2 downstream switch port can choose to accept or reject the request, depending on a
variety of conditions (refer to section L1 Entry Conditions on page 7-13). When accepting a request, the
PES32NT24xG2 downstream switch port sends continuous PM_Request_Ack DLLPs until the downstream
device receives these and sends an electrical idle ordered set, effectively placing the link in L1 state.
When rejecting a request, the PES32NT24xG2 downstream switch port sends a single
PM_Active_State_Nak TLP. The downstream device, upon reception of this TLP, should place its trans-
mitter into the L0s state, and exit this state prior to sending a new L1 ASPM entry request. Optionally, the
downstream device may keep the link in L0 state, in which case it must wait at least 10 µ s before sending a
new L1 ASPM entry request.
Some endpoint devices do not meet the required 10 µ s gap between consecutive L1 ASPM entry
requests. A live-lock situation can develop in the following scenario:
The Endpoint sends continuous PM_Active_State_Request_L1 DLLPs to the downstream
switch port of a switch.
The switch receives the request but decides to reject (i.e., due to a TLP already queued for
transmission on this link). The switch sends a PM_Active_State_Nak TLP to the endpoint
device.
The endpoint device notices the rejection, waits an amount of time (i.e., 8 µ s) and resumes
transmission of PM_Active_State_Request_L1 DLLPs.
The switch receives PM_Active_State_Request_L1 DLLPs, but does not recognize them as a
new L1 ASPM entry request, since there was a violation of the 10 us gap between L1 ASPM
entry requests.
The switch does not respond with an acceptance or rejection. Therefore, the endpoint keeps
waiting for an acceptance or rejection. A deadlock condition develops.
To avoid this deadlock condition, PES32NT24xG2 downstream switch ports allow programmability of a
timer that checks for the 10 µ s gap between L1 ASPM entry requests. There is a timer per port. The
Minimum Time between L1 Entry Requests (MTL1ER) field in the L1 ASPM Rejection Timer Control
(L1ASPMRTC) register may be programmed for this purpose.