IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 3 / 744

Notes
PES32NT24xG2 User Manual 1 January 30, 2013
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About This Manual
Overview
This user manual includes hardware and software information on the 89HPES32NT24xG2, a member of
IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect
standard. The part number PES32NT24xG2 which is used extensively throughout this manual in fact
covers two distinct switch devices: the PES32NT24AG2 and the PES32NT24BG2. The information in this
manual applies equally to both devices except where noted in occasional notes and footnotes in various
chapters.
Finding Additional Information
Information not included in this manual such as mechanicals, package pin-outs, and electrical character-
istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com)
as well as through your local IDT sales representative.
Content Summary
Chapter 1, “PES32NT24xG2 Device Overview,” provides an introduction to the performance capabili-
ties of the 89HPES32NT24xG2 and a high level architectural overview of the device.
Chapter 2, “Clocking,” provides a description of the PES32NT24xG2 clocking architecture.
Chapter 3, “Reset and Initialization,” describes the PES32NT24xG2 reset operations and initialization
procedure.
Chapter 4, “Switch Core,” provides a description of the PES32NT24xG2 switch core.
Chapter 5, “Switch Partitions,” describes how the PES32NT24xG2 supports up to 16 active switch
partitions.
Chapter 6, “Failover,” provides a description of the flexible failover mechanism that allows the
construction of highly-available systems.
Chapter 7, “Link Operation,” describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.
Chapter 8, “SerDes,” describes basic functionality and controllability associated with the Serialiazer-
Deserializer (SerDes) block in PES32NT24xG2 ports.
Chapter 9, “Power Management,” describes the power management capability structure located in the
configuration space of each PCI-to-PCI bridge in the PES32NT24xG2.
Chapter 10, “Transparent Operation,” describes the device-specific architectural features for the
transparent switch associated with each PES32NT24xG2 partition (i.e., the PCI-to-PCI bridge functions and
their interaction in the switch).
Chapter 11, “Hot-Plug and Hot-Swap,” describes the behavior of the hot-plug and hot-swap features
in the PES32NT24xG2.
Chapter 12, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the
PES32NT24xG2.
Chapter 13, “General Purpose I/O,” describes how the 9 General Purpose I/O (GPIO) pins may be
individually configured as general purpose inputs, general purpose outputs, or alternate functions.
Chapter 14, “Non-Transparent Operation,” describes how a non-transparent bridge in the
PES32NT24xG2 allows two roots or PCI Express trees (i.e., hierarchies) to be interconnected with one or
more shared address windows between them.