IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 513 / 744

IDT NT Endpoint Registers
PES32NT24xG2 User Manual 22 - 21 January 30, 2013
Notes
PCIELSTS - PCI Express Link Status (0x052)
6 CCLK RW 0x0 Common Clock Configuration.
When set, this bit indicates that this port and the port at the
opposite end of the link are operating with a distributed
common reference clock.
When a port operates in a multi-function mode, software
must set this bit identically for all functions of the port. Oth-
erwise, the port assumes that it is not operating with a dis-
tributed common reference clock.
After modifying this bit in both components of the link, soft-
ware must trigger a link retrain by setting the link retrain bit
in the upstream component’s Link Control register.
In the switch, the L0s and L1 exit latencies do not change
among common and non-common clock configurations.
7 ESYNC RW 0x0 Extended Sync.
When set this bit forces transmission of additional ordered
sets when exiting the L0s state and when in the recovery
state.
When a port operates in a multi-function mode, the effect of
this bit is applied when this bit is set in any of the port’s
functions.
8 CLKP-
WRMGT
RO 0x0 Enable Clock Power Management.
The device does not support this feature.
9 HAWD RO 0x0 Hardware Autonomous Width Disable.
Device ports do not have a hardware autonomous mecha-
nism to change link width, except due to link reliability
issues. Therefore, this bit is not applicable and is hardwired
to zero.
10 LBWINTEN RO 0x0 Link Bandwidth Management Interrupt Enable.
Not applicable.
11 LABWINTEN RO 0x0 Link Autonomous Bandwidth Interrupt Enable.
Not applicable.
15:12 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
3:0 CLS RO 0x1 Current Link Speed.
This field indicates the current link speed of the port.
1 -
(gen1) 2.5 GT/s
2 - (gen2) 5 GT/s
others - reserved
Bit
Field
Field
Name
Type
Default
Value
Description