IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 708 / 744

IDT JTAG Boundary Scan
PES32NT24xG2 User Manual 25 - 10 January 30, 2013
Notes
Therefore, instead of having to shift many times to get a value through the device, the user only needs to
shift one time to get the value from JTAG_TDI to JTAG_TDO. When the TAP controller passes through the
CAPTURE-DR state, the value in the BYPASS register is updated to be 0.
CLAMP
This instruction, listed as optional in the IEEE 1149.1 JTAG Specifications, allows the boundary scan
chain outputs to be clamped to fixed values. When the clamp instruction is issued, the bypass register is
selected between TDI and TDO and the scan chain passes through this register to devices further down-
stream.
IDCODE
The IDCODE instruction is automatically loaded when the TAP controller state machine is reset either by
the use of the JTAG_TRST_N signal or by the application of a ‘1’ on JTAG_TMS for five or more cycles of
JTAG_TCK as per the IEEE Std. 1149.1 specification. The least significant bit of this value must always be
1. Therefore, if a device has a Device ID register, it will shift out a 1 on the first shift if it is brought directly to
the SHIFT-DR TAP controller state after the TAP controller is reset. The board- level tester can then
examine this bit and determine if the device contains a Device ID register (the first bit is a 1), or if the device
only contains a BYPASS register (the first bit is 0).
However, even if the device contains a Device ID register, it must also contain a BYPASS register. The
only difference is that the BYPASS register will not be the default register selected during the TAP controller
reset. When the IDCODE instruction is active and the TAP controller is in the Shift-DR state, the thirty-two
bit value that will be shifted out of the Device ID register is shown in Figure 25.6.
VALIDATE
The VALIDATE instruction is automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits ‘01’ are mandated by the IEEE Std.
1149.1 specification.
EXTEST_TRAIN
EXTEST_TRAIN instruction listed and explained in the IEEE 1149.6 JTAG specification. It is used to test
AC pins during boundary scan by shifting data from TDI to TDO within the Shift-DR-TAP controller State.
This instruction becomes effective on the falling edge of TCK in the Update-IR state.
Bit(s) Mnemonic Description R/W Reset
0 Reserved Reserved R 0x1
11:1 Manuf_ID Manufacturer Identity (11 bits)
This field identifies the manufacturer as IDT. R 0x33
27:12 Part_number Part Number (16 bits)
This field identifies the silicon as PES32NT24AG2. R 0x808C
This field identifies the silicon as PES32NT24BG2. R 0x808A
31:28 Version Version (4 bits)
This field identifies the silicon revision of the
PES32NT24xG2. R silicon-
dependent
Table 25.4 System Controller Device Identification Register
Device Version Part Number Mnfg. ID LSB
PES32NT24AG2 xxxx 1000|0000|1000|1100 0000|0011|0011 1
PES32NT24BG2 xxxx 1000|0000|1000|1010 0000|0011|0011 1
Figure 25.6 Device ID Register Format