IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 83 / 744

IDT Switch Core
PES32NT24xG2 User Manual 4 - 5 January 30, 2013
Notes
sustaining full bandwidth throughput on a x4 Gen2 link and may be shared by four x1 ports, two x2 ports, or
one x4 port. Two memory modules are used for an x8 Gen2 port. The PES32NT24xG2 switch core contains
eight ingress memory modules and eight egress memory modules as shown in Figure 4.1.
The crossbar has ten ingress data interfaces (i.e., eight for ingress memory modules plus two for DMA
modules) and ten egress data interfaces (i.e., eight for egress memory modules plus two for DMA
modules).
The crossbar ingress and egress data pathways are sized at 160 bits. Given that a x8 Gen2 port has a
throughput of 128 bits per cycle, the crossbar has 20% “overspeed”. This overspeed compensates for the
contention experienced by ports whose IFBs or EFBs share a memory module.
Virtual Channel Support
All PES32NT24xG2 ports support one virtual channel (i.e., VC0). In all port operating modes, function 0
of the port contains a VC Capability Structure that provides architected port arbitration and TC/VC mapping
for VC0. Depending on the port operating mode, function 0 of the port may be a PCI-to-PCI bridge or NT
function.
TLPs received by a port from the link are subjected to TC/VC mapping prior to being stored in the port’s
IFB. TLPs whose traffic class does not map to VC0 are treated as malformed TLPs by the port and logged
as such in all functions of the port. Such TLPs are nullified prior to entering the IFB.
TLPs stored in the port’s EFB are also subjected to TC/VC mapping prior to being transmitted on the
link. TLPs whose traffic class does not map to VC0 are treated as malformed TLPs by the port and logged
as such in all functions of the port. Such TLPs are nullified prior to being transmitted on the link.
Packet Routing Classes
As mentioned above, the switch core is responsible for transferring packets among ports. As packets
are received from the PCI Express link, the ingress stack’s application layer determines the packet route
and sends this information to the switch core in the form of a packet descriptor.
From a switch core perspective, packet transfers among ports may be categorized as:
– Route-to-Self transfers (transfers from a port to itself)
– Port-to-port transfers (transfers among different ports)
Route-to-self transfers are implemented to process configuration requests that target the port, as well as
for proprietary internal control messaging between the ingress and egress logic of the port. Port-to-port
transfers are used for traffic routing of PCI Express TLPs, as well as for proprietary internal control
messaging among ports. The DMA modules are treated as any other port from a switch core’s perspective.
The PES32NT24xG2 is a partitionable PCI Express switch, meaning that ports may be partitioned into
groups that logically operate as completely independent switches. In addition, the switch supports non-
transparent bridging which allows the transfer of packets among partitions. Thus, port-to-port transfers may
be further categorized as:
– Transfers among ports in the same partition (intra-partition transfers)
– Transfers among ports in different partitions (inter-partition transfers)
Intra-partition transfers occur among switch ports that are logically in the same partition. These include
packet transfers from an upstream switch port to a downstream switch port, from a downstream switch port
to an upstream switch port, and among downstream switch ports.
Inter-partition transfers are logically done across the non-transparent-bridge formed by two NT
endpoints, one in each partition. Thus, an inter-partition transfer is logically received by the NT endpoint in
the packet’s source partition and transmitted by the NT endpoint in the packet’s destination partition.