IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 109 / 744

IDT Switch Partition and Port Configuration
PES32NT24xG2 User Manual 5 - 9 January 30, 2013
Notes
The port responds to received TLPs as follows:
– All received PCI Express configuration requests that do not target function 0 are completed with
a configuration-request-retry-status completion. The intent of this requirement is to prevent stan-
dard enumeration software from detecting the existence of port functions which may not be
present in the port after the partition is configured.
– All received requests that target function 0 but do not target function 0’s Global Address Space
Access Address or Data (GASAADDR or GASADATA) registers are completed with a configura-
tion-request-retry-status completion. The intent of this requirement is to prevent standard enumer-
ation of the unattached port by its root-complex.
• Function 0 responds to received PCI Express configuration requests that target the
GASAADDR and GASADATA normally (i.e., the requested action is performed and a comple-
tion is generated). A root-complex with customized switch configuration software may access
the switch global address space (and therefore all configuration registers in the device) by
accessing the GASAADDR and GASADATA registers in the unattached port. By accessing
the global address space, the root may reconfigure all ports and partitions in the switch.
– All other received requests are treated as unsupported requests (i.e., logging error status and if
appropriate, generating the appropriate completion). The generated completion (if any) has a
completer ID of zero.
– All registers in the port remain accessible from the global address space.
Configuration registers are accessible through the global address space by the serial EEPROM, other
ports, and the SMBus. Although the link in this mode behaves as an upstream port, all registers in the port’s
PCI-to-PCI bridge function take on the organization and initial values shown in Table 19.2 for a downstream
switch port.
Registers and fields in the PCI-to-PCI bridge function that affect the behavior of the link (listed below)
operate normally (i.e., control fields control behavior and status fields report status) as though the port were
an upstream port.
– PCIELCTL (all fields related to link/phy)
– PCIELSTS (all fields related to link/phy)
– PCIELCTL2 (all fields related to link/phy)
– PCIELSTS2 (all fields related to link/phy)
– SERDESCFG
– LANESTS[1:0]
– PHYPRBS
PCI-to-PCI bridge function registers other than those listed above operate as though the port were a
downstream switch port and take on the initial value of a downstream switch port. A port in this mode is
unaffected by the following:
– The reception of TS1 ordered-sets indicating a hot reset.
– The data link layer of the port transitioning to the DL_Down state.
– The reception of a Set_Slot_Power_Limit message.
Since the link operates as an upstream port (i.e., downstream component), an automatic speed change
is not initiated when the link enters L0. Automatic speed change may be enabled by modifying the value of
the Initial Link Speed Change Control (ILSCC) bit in the port’s Phy Link Configuration 0 (PHYLCFG0)
register.
Upstream Switch Port
A port in upstream switch port mode is composed of a PCI-to-PCI bridge function and has the following
behavior.
– Behaves as an upstream switch port as defined in the PCI Express Base Specification.
• All port output signals associated with downstream switch port operation are placed in a
negated state (i.e., hot-plug signals). The negated value of PxAIN, PxILOCKP, PxPEP, PxPIN,
and PxRSTN is determined as shown in Table 11.2.
– The LTSSM is operational and behaves as an upstream port.