IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 640 / 744

IDT DMA Function Registers
PES32NT24xG2 User Manual 23 - 52 January 30, 2013
Notes
DMAC[1:0]STS - DMA Channel Status (0x508/608)
9 DRNS RW 0x0 Descriptor Read No Snoop.
This field specifies the state of the no snoop attribute in
descriptor read operations.
10 DWRO RW 0x0 Descriptor Write Relaxed Ordering.
This field specifies the state of the relaxed ordering attribute
in descriptor write operations.
11 DWNS RW 0x0 Descriptor Write No Snoop.
This field specifies the state of the no snoop attribute in
descriptor write operations.
14:12 DTC RW 0x0 Descriptor Traffic Class.
This field specifies the traffic class used by descriptor read
and write operations.
15 Reserved RO 0x0 Reserved field.
17:16 DPREFETCH RW 0x0 DMA Descriptor Prefetch Level.
This field specifies the number of DMA descriptors that
DMA channel will attempt to prefetch.
0x0 - (disable) Disable DMA descriptor prefetching
0x1 -(one) Prefetch one DMA descriptor
0x2 - Reserved
0x3 - Reserved
31:18 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
0 F RW1C 0x0 Finished.
This bit is set when descriptor processing of a descriptor
with the IOF bit set completes normally.
Once set, this bit is never cleared by hardware.
1 A RW1C 0x0 Abort.
This bit is set when descriptor processing is aborted.
Once set, this bit is never cleared by hardware.
2 E RW1C 0x0 Error.
This bit is set when an unmasked channel error is detected
(i.e., an unmasked error bit in the DMACxERRSTS register
is set).
Initiation and resumption of DMA channel descriptor pro-
cessing is inhibited while this bit is set. See RUN bit defini-
tion in the DMACxCTL register.
Once set, this bit is never cleared by hardware.
3 C RW1C 0x0 Chain.
This bit is set when a descriptor chaining operation takes
place.
Once set, this bit is never cleared by hardware.
Bit
Field
Field
Name
Type Default
Value
Description