IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 727 / 744

IDT Usage Models
PES32NT24xG2 User Manual 26 - 17 January 30, 2013
Notes
• BUS = 0x0, DEV = 0x0, FUNC = 0x0, {EREG, REG} = 0xFF8
– Write the following values to the PTCTL1 register in the NT function in port 8 of switch #1:
• CFGTYPE = 0x0 (i.e., type 0 configuration access)
• OP = 0x1 (i.e., configuration write)
– Write the following value to the PTCDATA register in the NT function in port 8 of switch #1 switch:
• DATA = 0x3E100 (i.e., the address of the SWPORT0CTL register, which will be accessed indi-
rectly through the GASAADDR and GASADATA registers)
– The write to the PTCDATA causes switch #1 switch to send a type 0 configuration write request
to port 8 in switch #2.
• The requester ID is set to 0/0/4 (i.e., function 4 is used for punch-through requests).
• The completer ID is set to 0/0/0 (i.e., as determined by the PTCTL0 register.
• The configuration write request targets address 0xFF8 (i.e., as determined by the PTCTL0
register).
– Upon receiving the type 0 configuration write request, port 8 in switch #2 switch will write to the
register located at address 0xFF8 (i.e., the GASAADDR register). The value written to this register
is 0x3E100, which corresponds to the address of the SWPORT0CTL register in the global address
space of switch #2.
– To complete the sequence, the serial EEPROM must wait until the Punch Through Status
(PTCSTS) register reports that the punch through transfer has been completed correctly. To do
so, the serial EEPROM uses a “Wait” configuration block (see section Initialization from Serial
EEPROM on page 12-3) that stalls serial EEPROM execution until the DONE bit is set in the
PTCSTS register. Once the DONE bit is set in the PTCSTS register, the serial EEPROM proceeds
with the configuration sequence.
Using the same mechanism, the serial EEPROM can access the GASADATA register in the port 8 of
switch #2. By using the GASAADDR and GASADATA registers to access any register in switch #2, the
serial EEPROM can proceed to configure switch partitions in that switch.
The configuration of switch partitions in switch #2 could follow the sequence shown earlier for the parti-
tion configuration of switch #1.
Note that the root complex connected to switch #2 switch may start enumeration as soon as port 0 in
that switch is configured to upstream switch port with NT function mode. Also, note that the sequence
shown above configures the mode of port 0 (i.e., the port connected to the root complex) after all the other
ports are configured. In this way, the root complex is guaranteed to find a fully configured switch when it
enumerates.
Once the serial EEPROM configuration completes, switch #1 exits quasi-reset mode. Therefore, the root
complex associated with switch #1 proceeds to enumerate the switch.
After enumeration, the roots can proceed to configure the NT functions (i.e., in port 0 and port 8 of their
respective switches) and start communication across the NT crosslink. Since the NT function in port 8 of
each switch is not directly visible to each root complex, configuring the NT function in port 8 must be done
via the switch’s global address space (e.g., by accessing the GASAADDR and GASADATA registers in the
NT function in port 0).
DMA Usage Models
High-Performance Multiprocessor System
Goal
Describe the usage of the switch’s DMA and NT functions to create a high-performance multiprocessor
system.
Description
Fundamental reset is applied to the system. The switch in each processor node boots in switch-mode
“Multi-partition with Unattached ports”. Immediately after fundamental reset is applied, the system is as
shown in Figure 26.10.