IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 77 / 744

IDT Reset and Initialization
PES32NT24xG2 User Manual 3 - 13 January 30, 2013
Notes
components.
3. All logic associated with the switch partition (i.e., ports, switch core buffers, etc.) is logically reset to
its initial state.
4. All register fields and registers associated with the switch partition except those designated Sticky
and SWSticky, are reset to their initial value. The value of Sticky and SWSticky registers and fields
is preserved across a hot reset.
If the upstream port is a multi-function port, all functions of the port are affected by the hot reset.
5. As long as the condition that initiated the partition hot reset persists, logic associated with the parti-
tion remains at this step.
6. The port(s) associated with the partition begin to link train and normal partition operation begins.
The initiation of a hot reset due to the data link layer of the upstream port reporting a DL_Down status
may be disabled by setting the Disable Link Down Hot Reset (DLDHRST) bit in the corresponding Switch
Partition Control (SWPARTxCTL) register. When the DLDHRST is set and the upstream port’s data link is
down, the PHY LTSSM transitions to the appropriate states but the hot reset steps described above are not
executed. As a result, the behavior of the partition is the following:
– The upstream port’s function(s) are not reset and continue operation.
– TLPs destined to the partition’s upstream port link are handled as follows.
• TLPs received by the secondary side of the PCI-to-PCI bridge function, which are destined to
the upstream port’s link, are treated as unsupported requests by the function.
• TLPs received by an NT function in another partition, which are destined to the upstream link
associated with the NT function in this partition, are treated as unsupported requests by the NT
function that first received the TLP.
• The DMA function continues normal operation, but silently discards TLPs destined to the
upstream link.
– TLPs generated by the functions in the partition, and that are normally routed to the root (e.g.,
MSIs, INTx messages, PM_PME messages, etc.) are silently discarded.
– All transfers not destined to the partition’s upstream port link (e.g., peer-to-peer TLPs between
downstream switch ports, peer-to-peer TLPs between upstream port functions) continue to
operate normally.
Note that other hot reset trigger conditions (i.e., hot reset triggered by reception of training sets with the
hot reset bit set on the upstream port) are unaffected by the DLDHRST bit.
Partition Upstream Secondary Bus Reset
A partition upstream secondary bus reset is initiated by any of the following events.
– A one is written to the Secondary Bus Reset (SRESET) bit in the Bridge Control (BCTL) register
of the PCI-to-PCI bridge function in the partition’s upstream switch port
1
.
When an upstream secondary bus reset occurs, the following sequence of actions take place on logic
associated with the affected partition.
1. Each downstream switch port whose link is up propagates the reset by transmitting TS1 ordered sets
with the hot reset bit set.
If the link associated with a downstream switch port is in the Disabled LTSSM state, then a hot
reset will not be propagated out on that port. The port will instead transition to the Detect LTSSM
1.
Refer to section Switch Partitions on page 5-1 for a description of the port operating modes that are considered
upstream ports, downstream switch ports, upstream switch ports, etc.