IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 287 / 744

IDT Non-Transparent Switch Operation
PES32NT24xG2 User Manual 14 - 39 January 30, 2013
Notes
Note that the NT function in partition 2 logs the reception of the poisoned TLP reception, as well as the
reception of a completion TLP with UR status (i.e., the completion TLP logically generated by the down-
stream PCI-to-PCI bridge function in partition 2).
Error Emulation Control in the NT Function
The PES32NT24xG2 provides the capability to emulate error occurrence in the AER uncorrectable and
correctable error status registers. Associated with the NT function are two error emulation registers. The NT
function Uncorrectable Error Emulation (NTUEEM) and NT function Correctable Error Emulation
(NTCEEM) registers allow emulation of errors in the NT function.
When a bit in these registers is set, it causes the hardware to emulate the detection of the corre-
sponding error. The detection of the error is handled as shown in Figure 6-2 of the PCI Express 2.1 base
specification (i.e., the corresponding error is logged in the AER status registers (i.e., AERUES or AERCES),
and reported to the root-complex).
– To allow emulation of advisory errors, the NTUEEM register contains a bit named ADVISORYNF.
When this bit is set in conjunction with another bit in the NTUEEM register, the hardware flags the
error as an advisory error and handles it according to Figure 6-2 of the PCI Express 2.1 base spec-
ification. Refer to the description of this bit for details.
Since the error emulation does not involve an actual TLP, the AER Header Log registers
(AERHL[1:4]DW) in the switch have RWL type, such that they may be modified by software to emulate the
capturing of the TLP’s header.
Error Emulation Usage and Limitations
The following are some usage guidelines and limitations associated with error emulation.
– To emulate the detection of a correctable error:
• The desired error bit must be set in the NTCEEM register.
– To emulate the detection of an uncorrectable fatal error:
• The desired error bit must be set in the NTUEEM register.
• The severity of the error must be set to fatal in the AERUESV register.
– To emulate the detection of an advisory uncorrectable non-fatal error:
• The desired error bit must be set in the NTUEEM register. The error bit selected must qualify for
advisory handling as specified in the PCI Express 2.1 specification. Otherwise, the operation of
the emulation logic is undefined.
• The ADVISORYNF bit must be set in the NTUEEM register.
• The severity of the error must be set to non-fatal in the AERUESV register.
NT Endpoint (Partition 2) Refer to row corresponding to ‘Poisoned TLP
received’ in Table 14.4. In the table, this NT
function is considered the “NT endpoint in the
destination partition”.
Additionally, refer to row corresponding to
‘Completion with UR status received’ in Table
14.4.
Upstream PCI-to-PCI Bridge (Partition 2) Refer to row corresponding to ‘Poisoned TLP
received’ error in Table 10.9.
Note that the bridge only logs parity error recep-
tion in the PCISTS register as it did not receive
the TLP directly from the link.
Downstream PCI-to-PCI Bridge
(Partition 2) Refer to row corresponding to ‘Unsupported
Request’ error in Table 10.9.
Function Error Logging
Table 14.10 Error Logging at Each Function for Poisoned TLP Example (Part 2 of 2)