IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 311 / 744

IDT DMA Controller
PES32NT24xG2 User Manual 15 - 23 January 30, 2013
Notes
It is possible to “in-line” request rate control information within a descriptor, using the Request Rate (RR)
and Request Rate Update (RRU) fields in a stride descriptor (see section Stride Control Descriptor on page
15-7). This allows control of the request rate depending on the bandwidth of the source and destination
devices associated with the DMA transfer.
– For example, software could build a descriptor list that transfers data from a high-bandwidth
source device (i.e., x8 Gen 2 root port) to a low-bandwidth destination device (x1 Gen 1 endpoint).
The descriptor list would start with a stride descriptor that controls parameters associated with the
transfer, including the request rate. This rate would be programmed to throttle DMA requests to
prevent congestion at the destination device and the PCI Express topology.
– In this same example, a second descriptor list is chained to the first one. This second list would
be programmed to transfer data between the high-bandwidth root port and a high-bandwidth
endpoint (i.e., x8 Gen 2). The second list would start with a stride descriptor that controls param-
eters associated with the transfer, and re-programs the request rate used by the DMA channel. In
this example, given that both the source and destination devices have the same bandwidth, the
request rate would be disabled by setting the request rate to a value of zero (i.e., the DMA channel
would not throttle its requests).
DMA Multicast
A DMA channel may be configured such that the destination address of a descriptor hits a multicast
BAR aperture
1
in the upstream port’s PCI-to PCI bridge (i.e., transparent multicast) and/or in the NT func-
tion (non-transparent multicast). When this occurs, the posted TLP emitted by the DMA function is trans-
ferred to the upstream port’s link (i.e., the port where the DMA function resides), as well as multicasted to
the appropriate ports, as dictated by transparent and non-transparent multicast operation.
– In some systems, it may not be desired that the posted TLPs emitted by the DMA be transferred
on the upstream port’s link in addition to being multicasted to the appropriate ports in the switch.
The Multicast Receive Interpretation (MCRCVINT) register in the DMA function’s configuration
space may be programmed to control this behavior. Refer to the definition of this register for
details.
Figure 15.12 shows an example of the path taken by a posted TLP emitted by the DMA that falls in the
multicast BAR aperture of the upstream port’s PCI-to-PCI bridge function (assuming that the MCRCVINT
register is set to 0x0). As shown in the figure, the TLP is transmitted on the upstream port’s link, as well as
multicasted to the appropriate downstream ports.
Figure 15.13 shows a similar example, but this time the TLP emitted by the DMA is NT multicasted to
ports in other partitions. As shown in the figure, the TLP is transmitted on the upstream port’s link, as well
as NT multicasted to ports in other partitions.
Note that the behavior for TLPs that are multicasted differs from unicast transfers generated by the
DMA. Unicast TLPs, when claimed by an upstream port’s function (e.g., PCI-to-PCI bridge or NT), only
target this function. If not claimed by any of the upstream port functions, the TLP is sent on the upstream
link only.
DMA multicast allows the DMA to be configured to read data from a source location, and multicast this
data to several destination locations, thereby improving the performance of the transfer operation.
1.
Refer to Chapter 17 for details on multicast operation. Multicast operation only applies to posted TLPs.