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IDT PCI Express 89HPES32NT24xG2 User Manual Download Page 136

IDT   Link Operation

PES32NT24xG2 User Manual

7 - 8

January 30, 2013

Notes

When operating at 5.0 GT/s, a PES32NT24xG2 port initiates a link speed downgrade in the following

cases:

–

When the PHY layer cannot achieve reliable operation at the higher speed. In this case, the
PES32NT24xG2 port continues to support the higher speed in the training-sets it transmits during
link training.

–

When software sets the target link speed to 2.5 GT/s and sets the LRET bit in the port’s PCIELCTL
register. In this case, the PES32NT24xG2 port removes support for the higher speed in the
training-sets it transmits during link training.

Additionally, the PES32NT24xG2 ports always respond to link partner requests to change speed. In this

case, the speed change is only successful when both components in the link advertise support the target
speed. When a link speed upgrade operation fails, the PHY LTSSM reverts back to the speed before the
upgrade (i.e., 2.5 GT/s) and does not autonomously initiate a subsequent link speed upgrade. In this case,
the PHY continues to support Gen 1 and Gen 2 data rates and therefore responds to link partner requests
for link speed upgrade, or to link speed upgrades triggered by software setting the LRET bit in the port’s
PCIELCTL register.

PES32NT24xG2 ports do not have a mechanism to autonomously regulate link speed. As a result, the

Hardware Autonomous Speed Disable (HASD) bit in the PCIELCTL2 register has no effect and is hardwired
to 0x0. Additionally, the PES32NT24xG2 ports never set the ‘Autonomous Change’ bit in the training sets

exchanged with the link partner during link training

1

. Still, a link partner connected to a PES32NT24xG2

downstream switch port may autonomously change link speed. When this occurs, the PES32NT24xG2
downstream switch port sets the Link Autonomous Bandwidth Status (LABWSTS) bit in the PCIELSTS
register.

A system designer may limit the maximum speed at which each port operates by changing the target

link speed via software or EEPROM and forcing link retraining. Refer to section Link Retraining on page 7-9
for further details.

Software Management of Link Speed

Software can interact with the link control and status registers of downstream switch ports to set the link

speed, as well as receive notification of link speed changes. This gives software the capability to choose
the desired link speed based on system specific criteria. For example, depending on the traffic load
expected on a link, software can choose to downgrade link speed to 2.5 GT/s in order to reduce power on a
low-traffic link, and later upgrade the link to 5.0 GT/s when the bandwidth is required. Software may also
choose to change the link speed due to link reliability reasons (i.e., a link that has reliability problems at 5.0
GT/s may be downgraded to 2.5 GT/s).

As mentioned above, the Target Link Speed (TLS) field of the Link Control 2 Register (PCIELCTL2) in

function 0 of the port sets the preferred link speed. By default, the Target Link Speed of each switch port is
set to 5.0 GT/s. 

During normal operation, the link speed of a downstream switch port may be modified by setting the TLS

field in the PCIELCTL2 register to the desired speed and initiating link retraining by writing a one to the Link
Retrain (LRET) bit in the Link Control (PCIELCTL) register.

–

The port will only initiate a change to a higher speed if the link partner advertised support for the
higher speed in its latest entry to the Configuration.Complete or Recovery.RcvrCfg states.

–

If a speed change is initiated to a speed not supported by the link partner, then the port will remain
at the current speed by transitioning through the Recovery state without the “Speed_Change” bit
set.

Notification of link speed changes if provided through the link bandwidth notification mechanism

described in the PCI Express Base Specification. This mechanism is enabled by setting the Link Bandwidth
Management Interrupt Enable (LBWINTEN) bit in the PCIELCTL register of switch downstream switch
ports.

1. 

Note that the ‘Autonomous Change’ bit is located in bit 6 of the fourth symbol in the training sets. This bit has 

multiple meanings depending on the LTSSM state in which it is issued. The switch never sets this bit in LTSSM 
states in which this bit carries the ‘autonomous change’ meaning.

Summary of Contents for PCI Express 89HPES32NT24xG2

Page 1: ...reek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2013 Integrated Device Technology Inc IDT 89HPES32NT24xG2 PCI Express Switch User Manua...

Page 2: ...PLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPE...

Page 3: ...hapter 5 Switch Partitions describes how the PES32NT24xG2 supports up to 16 active switch partitions Chapter 6 Failover provides a description of the flexible failover mechanism that allows the constr...

Page 4: ...a descrip tion of each bit in those registers Chapter 24 Switch Control Registers lists the switch control and status registers in the PES32NT24xG2 and provides a description of each bit in those reg...

Page 5: ...lways the most significant bit and bit 0 is the least significant bit In double words bit 31 is always the most significant bit and bit 0 is the least significant bit In words bit 15 is always the mos...

Page 6: ...l automatically cause the register bits to be reset to zero Writes cause the register bits to be modified Reserved Reserved The value read from a reserved register bit is undefined Thus software must...

Page 7: ...value of 1 by a hardware event To clear a RW1C bit i e change its value to zero a value of one must be written to the location An RW1C bit is never cleared by hardware Read and Write when Unlocked So...

Page 8: ...ected Completions instead of Unsupported Requests and a new bullet was added at the top of section Address Routed TLPs In Chapter 14 modified text in Overview section and in section Unsupported Reques...

Page 9: ...in Description of NXTPTR in PCIEVCECAP register revised information for fields PARBC and PATBLOFF in VCR0CAP register revised information for fields LPAT and PARBSEL in VCR0CTL register revised Descri...

Page 10: ...ALL bit In Chapters 22 and 23 deleted references to SSIGNAL field In Chapter 25 added section Internal Switch Timers with 4 new registers and deleted SSIGNAL register Updated Figure 20 5 and Table 20...

Page 11: ...rt Operating Modes 1 3 Switch Partitioning 1 6 Non Transparent Operation 1 8 DMA Operation 1 12 Dynamic Reconfiguration and Failover 1 15 Switch Events 1 16 Multicasting and Non Transparent Multicasti...

Page 12: ...rors 4 16 Switch Core Time Outs 4 17 Memory SECDED ECC Protection 4 18 End to End Data Path Parity Protection 4 18 Reporting of Port AER Errors as Internal Errors 4 19 Switch Partition and Port Config...

Page 13: ...7 16 Crosslink 7 17 Hot Reset Operation on a Crosslink 7 17 Link Disable Operation on a Crosslink 7 18 Gen 1 Compatibility Mode 7 18 SerDes Overview 8 1 SerDes Numbering and Port Association 8 1 SerD...

Page 14: ...iew 11 1 Hot Plug Signals 11 3 Port Reset Outputs 11 5 Power Enable Controlled Reset Output 11 5 Power Good Controlled Reset Output 11 6 Hot Plug Events 11 7 Legacy System Hot Plug Support 11 7 Hot Sw...

Page 15: ...uests 14 18 Re programming the Bus Number of the NT Function 14 19 Interrupts 14 20 Virtual Channel Support 14 21 Maximum Payload Size 14 22 Power Management 14 22 Bus Locking 14 22 ECRC Support 14 22...

Page 16: ...s 16 5 Multicast Overview 17 1 Transparent Multicast Operation 17 1 Addressing and Routing 17 1 Usage Restrictions 17 6 Non Transparent Multicast Operation 17 6 NT Multicast Configuration 17 7 NT Mult...

Page 17: ...sters 21 28 Request Metering 21 32 WRR Port Arbitration Counts 21 33 Non Transparent Multicast Overlay 21 38 AER Error Emulation 21 40 Global Address Space Access Registers 21 43 NT Endpoint Registers...

Page 18: ...ntrol and Status Registers 24 1 Internal Switch Timers 24 5 Switch Partition and Port Registers 24 7 Failover Capability Registers 24 13 Protection 24 15 Switch Event Registers 24 16 Global Doorbells...

Page 19: ...stream Port Migration 26 8 Non Transparent Bridge NTB Usage Models 26 11 PES32NT24xG2 as a Multiprocessor System Interconnect 26 11 NT Crosslink NT Punch Through 26 15 DMA Usage Models 26 17 High Perf...

Page 20: ...IDT Table of Contents PES32NT24xG2 User Manual x January 30 2013 Notes...

Page 21: ...le 5 1 Port Functions for Each Port Operating Mode 5 7 Table 5 2 Port Operating Mode Changes Supported by the Switch 5 14 Table 7 1 Crosslink Port Groups 7 17 Table 7 2 Gen 1 Compatibility Mode bits c...

Page 22: ...Table 12 15 Pin Mapping of I O Expander 20 12 21 Table 12 16 Pin Mapping of I O Expander 21 12 22 Table 12 17 Slave SMBus Address 12 23 Table 12 18 Slave SMBus Command Code Fields 12 23 Table 12 19 CS...

Page 23: ...ble 15 12 PCI Express Errors Detected by the DMA Function s Transaction Layer 15 30 Table 15 13 Prioritization of Transaction Layer Errors 15 35 Table 19 1 Global Address Space Layout 19 1 Table 19 2...

Page 24: ...IDT List of Tables PES32NT24xG2 User Manual xiv January 30 2013 Notes...

Page 25: ...g Connection for a Port in Global Clocked Mode Non Common Clocked Configuration 2 4 Figure 2 5 Clocking Connection for a Port in Local Port Clocked Mode in a Common Clocked Configuration 2 5 Figure 2...

Page 26: ...abled 12 28 Figure 12 14 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled 12 28 Figure 12 15 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled 12 28 F...

Page 27: ...Figure 26 2 PES24NT6AG2 with Ports Operating in Different Clock Modes 26 3 Figure 26 3 PES16NT8BG2 with Two Partitions Configured via Serial EEPROM 26 4 Figure 26 4 PES16NT8BG2 with Two Partitions Con...

Page 28: ...IDT List of Figures PES32NT24xG2 User Manual xviii January 30 2013 Notes...

Page 29: ...R Header Log 1st Doubleword 0x11C 22 43 AERHL1DW AER Header Log 1st Doubleword 0x11C 23 36 AERHL2DW AER Header Log 2nd Doubleword 0x120 20 50 AERHL2DW AER Header Log 2nd Doubleword 0x120 22 43 AERHL2D...

Page 30: ...0x4A0 22 76 BARSETUP4 BAR 4 Setup 0x4B0 22 79 BARSETUP5 BAR 5 Setup 0x4C0 22 82 BARUTBASE0 BAR 0 Upper Translated Base Address 0x47C 22 70 BARUTBASE1 BAR 1 Upper Translated Base Address 0x48C 22 73 B...

Page 31: ...ion ROM Base 0x030 23 7 EROMBASE Expansion ROM Base Address Register 0x038 20 10 FCAP 3 0 CTL Failover Capability x Control 24 13 FCAP 3 0 STS Failover Capability x Status 24 14 FCAP 3 0 TIMER Failove...

Page 32: ...kup Table Lower Data 0x4E4 22 88 LUTMDATA Lookup Table Middle Data 0x4E8 22 89 LUTOFFSET Lookup Table Offset 0x4E0 22 88 LUTUDATA Lookup Table Upper Data 0x4EC 22 89 MAXLAT Maximum Latency 0x03F 22 12...

Page 33: ...Mask 0x408 22 55 NTINTSTS NT Endpoint Interrupt Status 0x404 22 54 NTMCC NT Multicast Control 0x900 21 38 NTMCG 3 0 PA NT Multicast Group x Port Association 0x600 60C 22 94 NTMCOVR 3 0 BARH NT Multic...

Page 34: ...ilities 2 0x06C 23 21 PCIELCTL PCI Express Link Control 0x050 20 21 PCIELCTL PCI Express Link Control 0x050 22 20 PCIELCTL PCI Express Link Control 0x050 23 16 PCIELCTL2 PCI Express Link Control 2 0x0...

Page 35: ...ification 0x008 23 4 RID Revision Identification Register 0x008 20 4 RMCOUNT Requester Metering Count 0x88C 21 33 RMCTL Requester Metering Control 0x880 21 32 S 7 0 CTL SerDes x Control 24 27 S 7 0 RX...

Page 36: ...lover Control 24 9 SWPART 7 0 STS Switch Partition x Status 24 8 SWPORT 23 0 CTL Switch Port x Control 24 9 SWPORT 23 0 FCTL Switch Port x Failover Control 24 12 SWPORT 23 0 STS Switch Port x Status 2...

Page 37: ...h other The main function of the NTB block is to initialize and translate addresses and device IDs to allow data exchange across PCI Express domains Note The part number PES32NT24xG2 covers two distin...

Page 38: ...bility should be adjusted to point to the next capability if necessary Device Serial Number Enhanced Capability The PES32NT24xG2 contains the mechanisms necessary to implement the PCI express device...

Page 39: ...section Stack Configuration on page 3 5 The DMA modules contain the logic and state asso ciated with DMA functionality DMA functionality is introduced below and described in detail in Chapter 15 DMA C...

Page 40: ...nt bridge between the port s PCI Express link and the switch s NT Interconnect Refer to section Non Transparent Operation on page 1 8 for details A port in upstream switch port with NT and DMA functio...

Page 41: ...ciated with a DMA function These are ports 0 and 8 Table 1 3 lists all the operating modes and their support by each port Ports marked with a blue dot support the corresponding operating mode The oper...

Page 42: ...ile the secondary side connects to the virtual PCI bus The primary side of a downstream port s PCI to PCI bridge is connected to the virtual PCI bus while the secondary side is associated with the ext...

Page 43: ...ing modes of the ports Boot time configuration may be performed via serial EEPROM external SMBus master or software executing on a root port e g BIOS OS driver or hyper visor Basic preconfigurations o...

Page 44: ...s Software executing on each hierarchy allocates PCI memory space to the BAR Memory opera tions that target a memory window defined by an NT endpoint are routed within the PCI domain to that endpoint...

Page 45: ...n which a non transparent bridge is integrated directly onto the virtual PCI bus The advantage of this approach is that it is simple to implement since the PCI to PCI bridge associated with a downstre...

Page 46: ...in either domain to communicate using the address windows presented by the NT endpoint BARs Functions may be connected to the upstream port e g the root or to a downstream switch port Upstream port T...

Page 47: ...int BARs Figure 1 9 Non Transparent Switch with Non Transparent Ports Figure 1 10 illustrates the switch configuration in which all ports are configured as NT endpoints Such a configuration may be use...

Page 48: ...Express hierarchy located in a switch partition s upstream port In each partition the operating mode of the switch s upstream port determines if this port contains a DMA function The following port op...

Page 49: ...imize latency i e the DMA need not read and buffer all the data prior to writing it to the target location Once processing is completed the DMA may be configured to issue an interrupt to the system Fi...

Page 50: ...ion in the target partition In such a configuration programming of the DMA would be typically done by an agent e g the CPU in the partition on which the DMA resides 1 This would allow the programming...

Page 51: ...tion may be initiated by software executing on a root complex or SMBus master or initiated by hardware as the result of a failover event The switch supports four failover configuration structures Each...

Page 52: ...function in other partitions For example in a switch configuration with two or more partitions the occurrence of a hot reset in a partition is an event that may be signaled to the root complex in oth...

Page 53: ...gister in the upstream port of the switch partition This causes a switch event and it s corresponding notification to other partitions In addition to the signaling there are dedicated data registers t...

Page 54: ...endpoints Figure 1 17 Example of Transparent Multicast In addition to transparent multicast the PES32NT24xG2 supports non transparent multicast a k a NT multicast NT multicast is a proprietary feature...

Page 55: ...tions In particular NT multicast has a proprietary address and requester ID overlay feature that allows the TLP s address and requester ID to be modified when emitted by the egress ports Such modifica...

Page 56: ...IDT PES32NT24xG2 Device Overview PES32NT24xG2 User Manual 1 20 January 30 2013 Notes...

Page 57: ...y internal switch logic e g switch core portion of a stack etc The PLL within each SerDes quad generates a 5 0 GHz clock used by the SerDes analog portion PMA and a 250 MHz clock used by the digital p...

Page 58: ...ifically ports that share a SerDes quad as shown in Figure 2 1 above must operate in the same clocking mode Ports that do not share a SerDes quad may operate in different clocking modes Each row in Ta...

Page 59: ...defined by the PCI Express Base Specification 2 1 Each port may independently be configured for common or non common reference clock configuration The grouping of ports shown in Table 2 1 above does...

Page 60: ...l reference clock GCLK used by the switch or the reference clock used by other ports As described in section Support for Spread Spectrum Clocking SSC on page 2 5 this separate reference clock can have...

Page 61: ...r local port clocking port 0 uses P00CLK as it s reference clock P02CLK becomes unused by the hardware and this clock should be connected to Vss on the system board Support for Spread Spectrum Clockin...

Page 62: ...Slot Clock Configuration SCLK field in each port s PCI Express Link Status PCIELSTS register The SCLK field controls the advertisement of whether or not the port uses the same reference clock frequen...

Page 63: ...al Clocked 1 common clocked Global Clocked 0 non common clocked 2 Global Clocked 0 non common clocked Global Clocked 1 common clocked 3 Global Clocked 1 common clocked Global Clocked 1 common clocked...

Page 64: ...ure Figure 2 4 Global Clocked don t care GCLK with SSC Different Refclk than the switch No Violates PCI Express 300 ppm clock difference requirement Local Port Clocked PxCLK GCLK Same PxCLK as the swi...

Page 65: ...t ends prior to that causing the low priority reset then the device partition port immediately transitions to the reset associated with low priority reset condition If the high priority and low priori...

Page 66: ...ve SMBus address is specified by the SSMBADDR 2 1 signals in the boot configuration vector 8 Within 20 ms after the switch fundamental reset condition clears the reset signal to the stacks is negated...

Page 67: ...respond to configuration request transactions within 100ms from the end of Conventional Reset cold warm or hot Additionally the PCI Express Base Specification indicates that a device must respond to c...

Page 68: ...plex initialization As noted in table Table 3 2 some of the initial values specified by the boot configuration vector may be overridden by software serial EEPROM or an external SMBus device See sectio...

Page 69: ...tware to read and write registers internal to the device before normal device opera tion begins The device exits the quasi reset state when the RST HALT bit is cleared in the SWCTL register by an SMBu...

Page 70: ...he corresponding stack e g STK0CFG controls the configuration of Stack 0 STK1CFG for Stack 1 etc Stack configurations not shown in the table are not allowed Programming the STKxCFG register to values...

Page 71: ...x2 0xC 0b01100 x1 x1 x2 x4 0xD 0b01101 x1 x1 x1 x1 x4 0xE 0b01110 x2 x1 x1 x2 x2 0xF 0b01111 x1 x1 x2 x2 x2 0x10 0b10000 x2 x2 x1 x1 x1 x1 0x11 0b10001 x2 x1 x1 x1 x1 x2 0x12 0b10010 x2 x1 x1 x1 x1 x1...

Page 72: ...Hex Binary P23 P22 P21 P20 P19 P18 P17 P16 0x0 0b00000 x8 0x1 0b00001 x4 x4 0x2 0b00010 x2 x2 x4 0x3 0b00011 x2 x2 x2 x2 0x6 0b00110 x4 x2 x2 0x8 0b01000 x4 x1 x1 x2 0x9 0b01001 x4 x1 x1 x1 x1 0xA 0b0...

Page 73: ...onfigurations 0x0 through 0x3 may be selected statically Other configurations must be selected dynamically see section Dynamic Reconfigura tion of a Stack via EEPROM SMBus below For Stacks 2 and 3 the...

Page 74: ...r port device number in downstream ports1 In these modes the best case latency across the switch is reduced by 12 ns The reduced latency modes are suitable for users who do not wish to reconfigure por...

Page 75: ...sociated with a switch partition e g master SMBus slave SMBus A partition reset may be subdivided into four subcategories partition fundamental reset partition hot reset partition upstream secondary b...

Page 76: ...ociated with the partition enter the Detect state 3 All registers and fields except those designated as SWSticky take on their initial value The value of SWSticky registers and fields is preserved acr...

Page 77: ...eived by an NT function in another partition which are destined to the upstream link associated with the NT function in this partition are treated as unsupported requests by the NT function that first...

Page 78: ...r of the PCI to PCI bridge function in a downstream switch port When a downstream secondary bus reset occurs the following sequence of actions take place on logic associated with the affected partitio...

Page 79: ...ngress buffer After undergoing ordering and arbitration they are transferred to the corresponding egress buffer via the crossbar interconnect The presence of egress buffers provides head of line block...

Page 80: ...acket s route and subjects it to TC VC mapping If a valid mapping to VC0 is found the packet is then stored in the port s IFB together with its routing and handling information i e the packet s descri...

Page 81: ...he HOLB relief is temporary and only lasts until the congested egress port s EFB is full Under normal circumstances it is not expected that this scenario will occur in a system Each EFB consists of th...

Page 82: ...s a matrix of pathways capable of concurrently transferring data between all the memory modules associated with the port IFBs and EFBs as well as the two DMA modules As mentioned before the port IFBs...

Page 83: ...ket Routing Classes As mentioned above the switch core is responsible for transferring packets among ports As packets are received from the PCI Express link the ingress stack s application layer deter...

Page 84: ...d in the ingress buffer of each port are subject to arbitration as they are moved towards the target egress port The switch core performs all packet arbitration functions in the PES32NT24xG2 The follo...

Page 85: ...he corresponding port Depending on the operating mode of the port e g upstream switch port NT function port upstream switch port with DMA function etc function 0 of the port may be a PCI to PCI bridge...

Page 86: ...for packet transfers requested by port 2 towards port 0 and so on up to the number of ports in the device In addition the P24IC field contains the count value for packet transfers requested by the DMA...

Page 87: ...by packets as they are transferred across the switch Typically cut through occurs when a TLP is received on an ingress link whose bandwidth is greater than or equal to the bandwidth of the egress lin...

Page 88: ...of packet is in IFB x8 At least 75 of packet is in IFB x2 2 5 x2 x1 Always x4 At least 50 of packet is in IFB x8 At least 75 of packet is in IFB 5 0 x1 Always x2 At least 50 of packet is in IFB x4 At...

Page 89: ...t complex have a x8 link Memory read request TLPs are three or four DWords in size A single memory read request may result in up to 4 KB of completion data being returned to the requester Depending on...

Page 90: ...ectivity application similar situations may occur in system interconnect applica tions Figure 4 3 PCI Express Switch Static Rate Mismatch Request metering operation is illustrated in Figure 4 4 Figure...

Page 91: ...imation on page 4 14 The request metering counter is a 24 bit counter The count represents a fixed point 0 13 11 number i e an unsigned number with 13 integer bits and 11 fractional bits but is treate...

Page 92: ...e of non posted request as described below The request metering counter is a 24 bit counter that represents a fixed point 0 13 11 number i e an unsigned number with 13 integer bits and 11 fractional b...

Page 93: ...Otherwise if the number of required data DWords is greater than CNSTLIMIT then the completion size is estimated using OverheadDWords as described below OverheadDWords represents the number of DWords...

Page 94: ...cording of headers for uncorrectable internal errors When an uncorrect able internal error is reported by AER a header of all ones is recorded It is possible to control the reporting of internal error...

Page 95: ...plex Still the appropriate bit is logged in the IERRORSTS0 1 registers regardless of the setting of the CIE bit Figure 4 7 shows a logical representation of the internal error circuitry within each PE...

Page 96: ...bit error correction is not disabled when a double bit error is detected and a double bit error may result in one or more single bit corrections Associated with each port are five memories IFB control...

Page 97: ...or may have occurred locally at the port Reporting of Port AER Errors as Internal Errors In scenarios in which the PES32NT24xG2 switch is multi partitioned a need may exist to inform the root associa...

Page 98: ...rt s PAERSTS register Associated with the PAERSTS register is the software visible Port AER Mask PAERMSK register The PAERMSK register determines which bits in the PAERSTS register result in a notific...

Page 99: ...l Errors Internal Error Detection Logic PAERSTS not exposed to software PAERMSK Port 0 Port 1 Port 2 Port N Internal Error Detection Logic internal errors for this port only AER Error Detection Logic...

Page 100: ...IDT Switch Core PES32NT24xG2 User Manual 4 22 January 30 2013 Notes...

Page 101: ...partition has an associated ID The PES32NT24xG2 supports 8 switch partitions with IDs 0 through 7 A port is attached to a switch partition by setting the Switch Partition SWPART field in the corre sp...

Page 102: ...port associated with the partition When the US bit is set in the SWPARTxSTS register the Upstream Port ID USID field contains the port ID of the upstream port of the partition A switch partition with...

Page 103: ...may have at most one attached upstream port Associating more than one such port with a partition is considered a programming error and produces undefined results Partition State A partition may be in...

Page 104: ...h Partition Status SWPARTxSTS register is set when a state change begins The Switch Partition State Change Completed SCC bit in the Switch Port Status SWPORTxSTS register is set when a state change co...

Page 105: ...s a logical entity that represents a PCI Express link stack logic e g physical layer data link layer transaction layer configuration space for each function in the port etc and TLP queues i e port s i...

Page 106: ...functions present in each mode The operation of the PCI to PCI bridge function is described in detail in Chapter 10 The operation of the NT function is described in detail in Chapter 14 The operation...

Page 107: ...state e g link status and hot plug signals The negated value of PxAIN PxILOCKP PxPEP PxPIN and PxRSTN is determined as shown in Table 11 2 PxACTIVEN and PxLINKUPN are negated All input signals associ...

Page 108: ...register fields whose value is dependent on port mode i e upstream or downstream are configured to operate as a downstream switch port Unattached An unattached port is a port not associated with a swi...

Page 109: ...y the serial EEPROM other ports and the SMBus Although the link in this mode behaves as an upstream port all registers in the port s PCI to PCI bridge function take on the organization and initial val...

Page 110: ...fied using a PCI Express configuration write request then the modification takes place prior to the generation of a completion for the request Still the completion uses the old i e unmodified device n...

Page 111: ...ream port Since the link operates as an upstream port i e downstream component an automatic speed change is not initiated when the link enters L0 Automatic speed change may be enabled by modifying the...

Page 112: ...state i e hot plug signals The negated value of PxAIN PxILOCKP PxPEP PxPIN and PxRSTN is determined as shown in Table 11 2 PCI Express requests that do not target function 0 are completed with unsuppo...

Page 113: ...of values in the MODE SWPART or DEVNUM fields that do not modify the partition with which the port is associated result in the actions associ ated with an operating mode change e g OMCI and OMCC are...

Page 114: ...perating mode change depends on the following factors The reset action on the port as dictated by the OMA field in the port s SWPORTxCTL register The TLP traffic conditions on the port at the time the...

Page 115: ...ehavior TLPs received by the port from the link before the operating mode modification is initiated are treated in a manner consistent with the old operating mode of the port and if appropriate corre...

Page 116: ...rtition upstream secondary bus reset condition is removed The removal of a downstream switch port that is affected by a source partition upstream secondary bus reset has no effect on the source partit...

Page 117: ...g an upstream switch port from a partition has no effect on the L1 ASPM state of down stream switch ports associated with the partition PME Synchronization Removing a port from a partition has the eff...

Page 118: ...n the destination partition i e the hot reset opera tion continues normally on the other ports in the partition The added downstream switch port participates in the ongoing hot reset after the additio...

Page 119: ...er of its upstream switch port See the PCI Express Base Specification for details Adding an upstream switch port to a partition causes it to affect the L0s ASPM state of downstream switch ports in the...

Page 120: ...sti nation partition This may result in the generation of Assert_INTx and Deassert_INTx messages if the new aggregated state is different from that previously reported to the root Adding a downstream...

Page 121: ...ing behavior in addition to that specified by the common operating mode change behavior All states associated with the port are reset Registers associated with the port are reset to their initial valu...

Page 122: ...is set and the OMCC bit is set when the mode change completes The Secondary Failover Status SFAILOVER bit is set in the SWPORTxSTS register A failover event may also trigger a modification in the stat...

Page 123: ...occurs The PES32NT24xG2 contains multiple mechanisms to accomplish this If the reconfiguration is the result of a failover event the failover may be signaled by the device via the following mechanisms...

Page 124: ...IDT Switch Partition and Port Configuration PES32NT24xG2 User Manual 5 24 January 30 2013 Notes...

Page 125: ...EL field selects the failover capability Both fields are in the Switch Port x Control SWPORTxCTL register A partition is sensitive to a failover capability when the Failover Enable FEN bit is set and...

Page 126: ...s cleared the state of the corresponding FAILOVERx signal has no effect on the operation of the device The Failover Signal Polarity FSIGPOL bit in the FCAPxCTL determines how state changes in the FAIL...

Page 127: ...pe of failover is determined by the state of the Failover Mode FMODE field in the corresponding Failover Capability Status FCAPxSTS register If the current failover mode is primary then a secondary fa...

Page 128: ...IDT Failover PES32NT24xG2 User Manual 6 4 January 30 2013 Notes...

Page 129: ...port The merging of ports is controlled by the stack configuration registers as described in section Stack Configuration on page 3 5 When ports are merged the corresponding serial link pins i e PExRP...

Page 130: ...dynamically by the PHY The highest achievable link width is the minimum of The value of the MAXLNKWDTH field in the port s PCI Express Link Capabilities PCIELCAP register The number of consecutive lan...

Page 131: ...n 2 PExRP n 3 Switch lane 3 lane 2 lane 1 lane 0 b Port trains to x4 with lane reversal PExRP n PExRP n 1 PExRP n 2 PExRP n 3 Switch lane 0 lane 1 c Port trains to x2 without lane reversal PExRP n PE...

Page 132: ...ExRP n 5 PExRP n 6 PExRP n 7 Switch lane 0 lane 1 lane 2 lane 3 lane 4 lane 5 lane 6 lane 7 a Port trains to x8 without lane reversal PExRP n PExRP n 1 PExRP n 2 PExRP n 3 PExRP n 4 PExRP n 5 PExRP n...

Page 133: ...uration of link widths This optional capability allows both components of a link to dynamically downconfigure and upconfigure links based on implementation specific criteria such as power savings link...

Page 134: ...nt advertises its supported speeds via the Data Rate Identifier bits in the TS1 and TS2 training sets transmitted to its link partner during link training The PCI Express Base Specification permits a...

Page 135: ...cification Upstream ports do not automatically initiate link speed upgrade to Gen 2 The Initial Link Speed Change Control ILSCC bit in a port s PHYLCFG0 register controls whether the port automaticall...

Page 136: ...etraining on page 7 9 for further details Software Management of Link Speed Software can interact with the link control and status registers of downstream switch ports to set the link speed as well as...

Page 137: ...he LTSSM transitions through the Detect state in its retraining attempt The speed of the link is not necessarily changed as a result of link retraining A link that operates at 5 0 GT s will continue t...

Page 138: ...r 16 Switch Events In an upstream port a link down due to L2 L3 Ready does not cause a hot reset on the port L3 Link is completely unpowered and off Link Down A transitional link down pseudo state pri...

Page 139: ...ayer to the hot reset state e g upstream switch port link receives training sets with the hot reset bit set upstream switch port reports DL_Down upstream secondary bus reset or downstream secondary bu...

Page 140: ...ly exception to this case is TLPs emitted by the DMA function that map into the partition s multicast BAR aperture as these TLPs are routed to the port func tion s that claim the TLP as well as the po...

Page 141: ...met The port has a TLP or DLLP scheduled for transmission on the link A downstream switch port in the switch partition has initiated exit from L0s A port configured in downstream switch port mode init...

Page 142: ...for transmission on the link The port s EFB is empty The port has no DLLPs pending for transmission The port s receiver is idle i e no TLPs or DLLPs are received for the amount of time specified abov...

Page 143: ...nditions refer to section L1 Entry Conditions on page 7 13 When accepting a request the PES32NT24xG2 downstream switch port sends continuous PM_Request_Ack DLLPs until the downstream device receives t...

Page 144: ...ted In the L2 L3 Ready state the PES32NT24xG2 considers the link to be down The PxLINKUPN signal is therefore deasserted in this state The PxACTIVEN output is asserted whenever any TLP other than a ve...

Page 145: ...INKDIS bit in the port s Phy Link Configuration 0 PHYLCFG0 register Hot Reset Operation on a Crosslink When a PES32NT24xG2 port forms a crosslink hot reset operates as follows For a port operating in...

Page 146: ...with devices that conform to the PCI Express Base 1 1 or earlier specifications i e Gen 1 devices Specifically this mode overcomes the problem in which Gen 1 devices react incorrectly to newly define...

Page 147: ...exits Gen 1 Compatibility Mode by clearing the G1CME field in the PHYLCFG0 register and fully retraining the link i e via the FLRET bit the PHYLSTATE0 register When this occurs the training set bits...

Page 148: ...IDT Link Operation PES32NT24xG2 User Manual 7 20 January 30 2013 Notes...

Page 149: ...he ports in the switch and the SerDes quads with which they are associated The SerDes port association depends on the configuration of the corresponding stack1 as shown in the tables SerDes Port assoc...

Page 150: ...4 Lane 3 Lane 2 Lane 1 Lane 0 x4 x4 Port 6 Port 4 Lane 3 Lane 2 Lane 1 Lane 0 Lane 3 Lane 2 Lane 1 Lane 0 x2 x2 x2 x2 Port 7 Port 6 Port 5 Port 4 Lane 1 Lane 0 Lane 1 Lane 0 Lane 1 Lane 0 Lane 1 Lane...

Page 151: ...uring normal opera tion of the link or while the link is being tested By default the SerDes transmit level can be programmed in the range from 980 mV to 120 mV at steps of 15 mV each In addition there...

Page 152: ...to the transmitter controls described above the switch SerDes also contains a receiver equalizer to compensate for effects of channel loss on received signal i e high speed signal degradation due to t...

Page 153: ...e port For instance when port 0 is configured as a x4 port it is associated with SerDes quad 0 lanes 3 to 0 see Table 8 1 If the TM field in the port s PCIELCTL2 register is set to Normal Operating Ra...

Page 154: ...data rate with 3 5 dB de emphasis As the PHY changes data rate to Gen 2 the SerDes transmit settings are automatically modified to the values specified in the S x TXLCTL0 and S x TXLCTL1 registers cor...

Page 155: ...t for post silicon device characterization data Transmit Levels Settings of Relevant Fields in the S x TXLCTL0 S x TXLCTL1 Registers Drive Level mV De empha sis dB De empha sized Drive Level mV TDVL_F...

Page 156: ...0x3 0x0 811 3 0 574 0x14 0x3 0x3 0x0 794 3 0 562 0x13 0x3 0x3 0x0 776 3 0 550 0x12 0x3 0x3 0x0 750 3 0 529 0x11 0x3 0x3 0x0 724 3 1 508 0x10 0x3 0x3 0x0 699 3 1 487 0xF 0x3 0x3 0x0 673 3 2 467 0xE 0x3...

Page 157: ...ion data Transmit Levels Settings of Relevant Fields in the S x TXLCTL0 S x TXLCTL1 Registers Drive Level mV De empha sis dB De empha sizedDrive Level mV TDVL_FS6DBG2 CDC_FS6DBG2 FDC_FS6DBG2 TX_SLEW_G...

Page 158: ...ents on a per lane basis using the appropriate fields in the S x TXLCTL0 and S x TXLCTL1 registers Table 8 5 shows the register fields that control fine and coarse de emphasis for each PHY operating m...

Page 159: ...is controlled by the FDC_FS3DBG1 field in the S x TXLCTL0 register When the PHY operates in Gen 2 data rate with 3 5 dB de emphasis the fine de emphasis is controlled by the FDC_FS3DBG2 field in the S...

Page 160: ...rained by setting the LRET bit in the port s PCIELCTL register Low Swing Transmitter Voltage Mode PES32NT24xG2 ports support the optional low swing transmit voltage mode defined in the PCI Express Bas...

Page 161: ...silicon characterization Please refer to the device data sheet for post silicon device characterization data Drive Level mV TDVL_LSG1 671 0x0F 640 0x0E 609 0x0D 573 0x0C 537 0x0B 501 0x0A 465 0x09 426...

Page 162: ...power state depends on the state of the port s associated with the SerDes as described below When a port is disabled For a x4 or x8 port the SerDes quad s associated with the disabled port are placed...

Page 163: ...esponding SerDes Control S x CTL register Refer to the definition of this field for further details Powering down a SerDes shared by multiple ports results in all such ports being affected Refer to se...

Page 164: ...IDT SerDes PES32NT24xG2 User Manual 8 16 January 30 2013 Notes...

Page 165: ...ement capability structure associated with each function affects the power state of that function only The link s power state is derived from the power state of the function s in the port When a funct...

Page 166: ...unsupported requests UR Vendor Defined Type 1 messages are silently dropped From State To State Description any D0 Uninitialized Partition reset any type D0 Uninitialized D0 Active Function configured...

Page 167: ...ved by the function except as noted above are treated as unsupported requests UR Any error message resulting from the receipt of a TLP is reported in the same manner as when the function is not in D3h...

Page 168: ...eady state The PME_Turn_Off PME_TO_Ack protocol may be initiated by the root when the switch function s are in any power management state The port s handling of the power management fence protocol dep...

Page 169: ...PME_Turn_Off PME_TO_Ack handshake Finally note that the DMA function does not automatically quiesce traffic as a result of the PME_Turn_Off PME_TO_Ack handshake on the port It is the responsibility of...

Page 170: ...IDT Power Management PES32NT24xG2 User Manual 9 6 January 30 2013 Notes...

Page 171: ...r to Chapter 14 For details on the DMA operation refer to Chapter 15 Transaction Routing The PES32NT24xG2 PCI to PCI bridge functions support routing of all transaction types defined in PCI Express Ba...

Page 172: ...ing legacy software to run without modification on PCI Express Locked transactions are only supported between an upstream switch port i e PCI to PCI bridge function and a downstream switch port in the...

Page 173: ...onse from the locked device These transactions do not change the state of the bus locked partition Therefore a CplLk completion received by the downstream switch port of a bus locked partition in no w...

Page 174: ...tained in the PCI to PCI bridge function s MSIADDR and MSIADDRU registers to an address that does not route to the partition s upstream link and generating an MSI produces undefined results An MSI gen...

Page 175: ...he PES32NT24xG2 maintains an aggregated INTx state for each of the four inter rupt signals i e A through D at each port The aggregation includes INTx interrupts generated by all downstream ports of th...

Page 176: ...rt operating mode changes affect the aggregated INTx state of a partition Access Control Services The PCI to PCI bridge function supports Access Control Services ACS as defined in PCI Express Base Spe...

Page 177: ...o be re directed the re direction is implemented such that TLPs received by a port that are ACS re directed follow the ordering rules described in section Packet Ordering on page 4 6 The following fig...

Page 178: ...eam Forwarding Example Finally Figure 10 5 shows an example of ACS peer to peer request re direct at the PCI to PCI bridge function of a multi function upstream port As shown the offending TLP receive...

Page 179: ...request TLPs received by a downstream switch port on its ingress link ACS Upstream For warding 2 Applicable to request or completion TLPs received by the downstream switch port on its ingress link th...

Page 180: ...e only logged in functions in which ECRC checking is enabled Refer to section Error Detection and Handling by the PCI to PCI Bridge Function on page 10 11 for details on the logging and signaling of E...

Page 181: ...actions to log and report the error The terms uncorrectable error processing and correctable error processing refer to the processing described in Section 6 2 5 of PCI Express Base Specification Error...

Page 182: ...ors Error Condition PCI Express Base Specification1 Section 1 Refer to PCI Express Base Specification Rev 2 1 Function Specific Error Action Taken Bad TLP2 2 A Bad TLP is a TLP ending in EDB with LCRC...

Page 183: ...t in the same partition i e the TLP s bus device function destination ID matches that or the downstream port s PCI to PCI bridge function A downstream PCI to PCI bridge function that receives a TLP th...

Page 184: ...e error processing Advisory case correctable error processing Affected packet is forwarded across the bridge unless the bridge function is the target of the TLP in which case the TLP is dropped by thi...

Page 185: ...non advisory The Signaled Target Abort STAS bit is set in the PCISTS or SECSTS reg ister if the TLP was received on the function s primary or secondary side respectively Uncorrectable error processin...

Page 186: ...rt Link Down TLPs flowing downstream across a down stream switch port s PCI to PCI Bridge whose link is down Such TLPs are URed by the appropriate downstream switch port 2 2 9 1 1 NOTE Vendor Defined...

Page 187: ...0 Configuration read or write request LENGTH 1 doubleword TC 0 ATTR 0 Last DWord BE 3 0 0b0000 Message Requests interrupt message Power management message Error signaling message Unlock message Set po...

Page 188: ...is claimed by the PCI to PCI bridge function When the TLP is not received on the link header logging is not performed Reception of a TLP that causes a multicast blocking error see Chapter 17 Multicas...

Page 189: ...Advisory when the correspond ing error is con figured as non fatal in the AERUESV reg ister and an ACS violation is detected on a non posted request If TLP is a non posted request a completion with co...

Page 190: ...is superseded by a higher priority error Table 10 15 shows the prioritization of transaction layer errors used by the switch ports All errors listed in the table are associated with the reception of...

Page 191: ...detected handle per Table 13 9 but do not log UR error and do not generate a completion with UR status Else handle per Table 13 9 Yes Poisoned TLP If ECRC error detected handle per Table 13 9 but do n...

Page 192: ...ecks since the higher priority ECRC error does not inhibit the checking for multicast blocking errors In case the TLP with ECRC error is blocked by the multicast blocking check the blocking action tak...

Page 193: ...ccess Enable MAE bit must be set in the port s PCI Command PCICMD register For I O transactions the I O Access Enable IOAE bit must be set in the port s PCI Command PCICMD register MEM or IO TLPs rece...

Page 194: ...r Defined Type 0 message which targets an enabled switch port Vendor Defined Type 1 messages that target a switch port are silently discarded by that port Error Emulation Control in the PCI to PCI Bri...

Page 195: ...set in the P2PUEEM register The error bit selected must qualify for advisory handling as specified in the PCI Express 2 1 specification Otherwise the operation of the emulation logic is undefined The...

Page 196: ...IDT Transparent Switch Operation PES32NT24xG2 User Manual 10 26 January 30 2013 Notes...

Page 197: ...rd and the upstream port serves as the add in card s PCI Express interface In this application the upstream port may be hot plugged into a slot on the main system Finally Figure 11 3 illustrates the u...

Page 198: ...is implemented or on the add in board When located on the add in board state changes are communicated between the hot plug controller asso ciated with the slot and the add in card via hot plug messag...

Page 199: ...port Hot Plug Signals All PCI Express defined hot plug signals are supported on each port using low cost external I O expanders The switch requires these I O expanders for hot plug operation Table 11...

Page 200: ...the polarity of that signal to be inverted Inversion affects the corresponding signal in all ports When a one is written to the Electromechanical Interlock Control EIC bit in the port s PCI Express Sl...

Page 201: ...on fundamental reset then the PxPEP hot plug output remains asserted through the partition fundamental reset and does not glitch Following a partition hot reset a partition upstream secondary bus rese...

Page 202: ...ed as a side effect of slot power being turned on or off However the timing in this mode depends on the power good state of the slot s power supply The operation of this mode is illustrated in Figure...

Page 203: ...itions from not set to set Attention button pressed Power fault detected MRL sensor changed Presence detect changed Command completed event Data link layer state change event The PME Enable PMEE bit i...

Page 204: ...registers operate as normal and all other hot plug functionality associ ated with the port remains unchanged INTx MSI and PME events from other sources are also unaffected Hot Swap The switch is hot...

Page 205: ...SMBus master must be the only master in the SMBus lines that connect to the serial EEPROM and I O expander slaves In the split configuration the master and slave SMBuses operate as two independent bus...

Page 206: ...um of nine clock pulses 2 At each clock pulse when the MSMBCLK signal is high the master SMBus interface samples the MSMBDAT signal If the sampled value is a logic 1 then the next step is performed Ot...

Page 207: ...are interpreted as configuration blocks and sequential reading of the serial EEPROM continues until the end of a configuration done block is reached or the serial EEPROM address rolls over from 0xFFF...

Page 208: ...the double word initialization value Figure 12 2 Single Double word Initialization Sequence Format The second type of configuration block is the sequential double word initialization sequence It is si...

Page 209: ...ield in the Jump config uration block must specify a byte address that is greater than the address of the Jump configuration block itself For example a Jump configuration block at byte address 0x10 mu...

Page 210: ...be ignored Another configuration image i e configuration C is executed when the switch mode causes jump configuration blocks with jump code 0 to execute And the third configuration image i e configur...

Page 211: ...e EEPROM and internally polls the value of the register specified SYSADDR field in the Wait block When the value at this internal register matches the 32 bit data value in the Wait block masked bits d...

Page 212: ...he MODE SWPART or DEVNUM fields in the SWPORTxCTL register without modifying their values does not constitute a port operating mode change Care must be taken when using the Wait configuration block as...

Page 213: ...TL register A summary of possible errors during serial EEPROM initialization and specific action taken when detected is summarized in Table 12 3 The detection of any error causes the EEPROM Error Dete...

Page 214: ...n the SMBUSSTS register Abort initialization set EEPROMDONE bit in the SMBUSSTS register Invalid configuration block type Set RSTHALT bit in SWCTL register ICB bit is set in the SMBUSSTS register EED...

Page 215: ...e PCA9555 PCA9535 and PCA9539 See the Phillips PCA9555 data sheet for details on the operation of this device Note The MAX7311 is recommended since it is Phillips PCA9555 compatible and supports 64 s...

Page 216: ...ng I O expander by the PES32NT24xG2 to configure the device This configuration initializes the direction of each I O expander signal and sets outputs to their default value 9 Lower Port 13 hot plug Up...

Page 217: ...anders 12 and 13 i e the ones that contain MRL and partition fundamental reset inputs 1 Write value 0x0 to I O expander register 4 no inversion in IO 0 2 Write value 0x0 to I O expander register 5 no...

Page 218: ...is an open drain interrupt output that is asserted when an I O expander input pin changes state The open drain I O expander interrupt output of all I O expanders should be tied together on the board a...

Page 219: ...ions due to partition upstream secondary bus resets and partition hot resets I O expander outputs are not modified when the device transitions from normal operation to a fundamental reset In systems w...

Page 220: ...ally operated retention latch MRL input 4 I O 0 4 I P4MRLN Port 4 manually operated retention latch MRL input 5 I O 0 5 I P5MRLN Port 5 manually operated retention latch MRL input 6 I O 0 6 I P6MRLN P...

Page 221: ...notation used for PCA9555 port x I O pin y I P0ILOCKST Port 0 electromechanical interlock state input 1 I O 0 1 I P2ILOCKST Port 2 electromechanical interlock state input 2 I O 0 2 I P4ILOCKST Port 4...

Page 222: ...output 11 I O 1 3 O P7ILOCKP Port 7 electromechanical interlock output 12 I O 1 4 O P10ILOCKP Port 10 electromechanical interlock output 13 I O 1 5 O P14ILOCKP Port 14 electromechanical interlock outp...

Page 223: ...ut 1 I O 0 1 O P1LINKUPN Port 1 link up status output 2 I O 0 2 O P2LINKUPN Port 2 link up status output 3 I O 0 3 O P3LINKUPN Port 3 link up status output 4 I O 0 4 O P4LINKUPN Port 4 link up status...

Page 224: ...11 I O 1 3 O P11ACTIVEN Port 11 Link active status output 12 I O 1 4 O P12ACTIVEN Port 12 Link active status output 13 I O 1 5 O P13ACTIVEN Port 13 Link active status output 14 I O 1 6 O P14ACTIVEN P...

Page 225: ...notation used for PCA9555 port x I O pin y O P0RSTN Port 0 reset output 1 I O 0 1 O P2RSTN Port 2 reset output 2 I O 0 2 O P4RSTN Port 4 reset output 3 I O 0 3 O P6RSTN Port 6 reset output 4 I O 0 4 O...

Page 226: ...zed The address is specified by the SSMBADDR 2 1 1 signals as shown in Table 12 17 SMBus I O Expander Bit Type Signal Description 0 I O 0 0 1 1 I O x y corresponds to the notation used for PCA9555 por...

Page 227: ...interface is shown in Figure 12 9 and described in Table 12 18 Figure 12 9 Slave SMBus Command Code Format Address Bit Address Bit Value 1 SSMBADDR 1 2 SSMBADDR 2 3 1 4 0 5 1 6 1 7 1 Table 12 17 Slave...

Page 228: ...ent SMBus transaction 0 Packet error checking disabled for the current SMBus transaction 1 Packet error checking enabled for the current SMBus transaction Byte Position Field Name Description 0 CCODE...

Page 229: ...the Global Address Space Bit Field Name Type Description 0 BELL Read Write Byte Enable Lower When set the byte enable for bits 7 0 of the data word is enabled 1 BELM Read Write Byte Enable Lower Midd...

Page 230: ...Table 12 18 1 BYTECNT Byte Count The byte count field is only transmitted for block type SMBus transactions SMBus word and byte accesses to not contain this field The byte count field indicates the nu...

Page 231: ...tion when accessing the serial EEPROM This bit has the same function as the NAERR bit in the SMBUSSTS register The setting of this bit may indicate the following that the addressed device does not exi...

Page 232: ...END S Switch Slave SMBus Address Rd ADDRU A BYTCNT 5 A EEADDR CMD status A A A N DATA ADDRU A P ADDRL A S Switch Slave SMBus Address Wr A N CCODE START END P Switch not ready with data S Switch Slave...

Page 233: ...e must be realized and the bit fields for each byte sequence must be understood Tables 12 23 12 24 and 12 25 provide a description of the CSR byte sequence command code fields and CMD field respective...

Page 234: ...eld is only transmitted for block type SMBus transactions SMBus word and byte accesses do not contain this field The byte count field indicates the number of bytes following the byte count field when...

Page 235: ...ce 4 2 FUNCTION This field encodes the type of SMBus operation 0 CSR register read or write operation 1 Serial EEPROM read or write operation 2 through 7 Reserved 6 5 SIZE This field encodes the data...

Page 236: ...bit is set if the last CSR write SMBus transaction was not claimed by a device Success indicates that the transaction was claimed and not that the operation completed without error Constant Name Value...

Page 237: ...ck CCode_i 0x03 0x40 0x43 0x43 start bit 1 end bit 1 function_bits CSR size_bits BLOCK Index 1 Set the byte count BKCnt_i TranSize_BkWtHeader BKCnt_i 3 The byte count field indicates the number of byt...

Page 238: ...ader BKCnt_i 3 Index 2 Set the word option BELL and BELM and set the CSR READ operation OPRD BKCmd_i CMD_Init CMD_BELL CMD_BELM CMD_OPRD BKCmd_i 0x00 0x01 0x02 0x10 0x13 Index 3 Set the lower CSR regi...

Page 239: ...transaction size and read length TranSize TranSize_WtB4Rd 1 ReadLength length TranSize_BkRdHeader Examples of Setting Up the I2C CSR Byte Sequence for a CSR Register Write The following examples are...

Page 240: ...er of bytes following the byte count field when setting up for a write or setting up for a read Index 2 Set the byte option BELL and set the CSR WRITE operation clear OPRD bit BKCmd_i CMD_Init CMD_BEL...

Page 241: ...nt_i TranSize_BkWtHeader Len_Word BKCnt_i 3 2 5 Index 2 Set the word option BELL and BELM and set the CSR WRITE operation clear OPRD bit BKCmd_i CMD_Init CMD_BELL CMD_BELM BKCmd_i 0x00 0x01 0x02 0x03...

Page 242: ...Initialize the command code byte CCode_i CCode_Block CCode_i 0x03 0x40 0x43 In the Command Code 0x43 start bit 1 end bit 1 function_bits CSR size_bits BLOCK Index 1 Set the byte count BKCnt_i TranSize...

Page 243: ...5 Set the lower data byte BKDtL_i low byte of low word data BKDtL_i 0x11 of 0xBBAA2211 Index 6 Set the upper data byte BKDtL_i 1 high byte of low word data BKDtL_i 1 0x22 of 0xBBAA2211 Index 7 Set the...

Page 244: ...IDT SMBus Interfaces PES32NT24xG2 User Manual 12 40 January 30 2013 Notes...

Page 245: ...Table 13 1 summarizes the configuration of GPIO pins Input When configured as an input in the GPIOCFG register and as a GPIO function in the GPIOFUNC register the GPIO pin is sampled and registered i...

Page 246: ...uses PART0PERSTN to be internally held high GPIO Pin Alternate Function 0 Alternate Function 1 0 PART0PERSTN P16LINKUPN 1 PART1PERSTN P16ACTIVEN 2 PART2PERSTN P4LINKUPN 3 PART3PERSTN P4ACTIVEN 4 FAILO...

Page 247: ...IDT General Purpose I O PES32NT24xG2 User Manual 13 3 January 30 2013 Notes...

Page 248: ...IDT General Purpose I O PES32NT24xG2 User Manual 13 4 January 30 2013 Notes...

Page 249: ...NTB and the destination partition is the partition to which the TLP is destined The PES32NT24xG2 supports eight non transparent functions a k a NT functions or NT endpoints Each NT function appears as...

Page 250: ...an aperture with read only bits in the BADDR field the PCI architec ture only allows apertures to be requested that are a power of two in size In many applications it is desir able to allocate smaller...

Page 251: ...r than the BAR base address plus the power of two aperture size requested by the BAR disables the limit capability The aperture and effective aperture in this case are both equal to the power of two s...

Page 252: ...nt when accessing the NT function s configuration space memory mapped to BAR 0 TLP Translation Direct Address Translation All BARs may be configured to support direct address translation Figure 14 2 i...

Page 253: ...undefined results If both BARs two and four are configured for lookup table address translation then BAR two only supports a 12 entry lookup table Configuring BAR two for 24 entry lookup table address...

Page 254: ...5 Segments 0 to 11 are each associated with a lookup table entry in the lower half of the table e g segment 0 is associated with lookup table entry 0 segment 1 is associated with lookup table entry 1...

Page 255: ...ze of the address space translated by each table entry BARSETU Px SIZE Field Aperture Size Page Size Base Address bits 1 1 Assumes 64 bit TLP address If only 32 bits are used then bits 31 x are used I...

Page 256: ...the state of all lookup table fields except the Valid V field is undefined Following a switch fundamental reset the Valid field is cleared in all entries BARSETU Px SIZE Field Aperture Size Page Size...

Page 257: ...nt NT Mapping Table Associated with the switch is a 64 entry Non Transparent NT Mapping table The NT Mapping table is used to perform ID translation and ID based protection The NT Mapping table is a g...

Page 258: ...ATA or via the Extended Configuration Space Access registers i e ECFGADDR and ECFGDATA All other methods to access these registers are allowed i e PCI Express configuration requests that target the re...

Page 259: ...apping Table Status NTMTBLSTS register A protection violation during an NTMTBLDATA write operation causes the write operation to be ignored i e no table entry or register field is actually updated and...

Page 260: ...ers These unimplemented function numbers are referred to as phantom function numbers A requester that uses phantom function numbers when communicating with the NT endpoint requires a unique NT Mapping...

Page 261: ...he PCI Express hierarchy then the TLP is handled as an unexpected completion by the NT function Refer to section Error Detection and Handling by the NT Function on page 14 25 Otherwise the 8 bit value...

Page 262: ...s data payload is 1 DW with the upper 16 bits set to zero and the lower 16 bits reflecting the requester ID of the agent that issued the configuration read request The same opera tion is supported whe...

Page 263: ...not support Address Translation Services ATS as defined by the PCI SIG but it has the ability to modify the AT field for TLPs that cross the NTB This allows the NTB to receive TLPs with translated ad...

Page 264: ...to form a global doorbell request This global doorbell request is then used to initiate inbound door bell requests to each of the partitions An outbound doorbell may initiate inbound doorbell requests...

Page 265: ...ge registers is illustrated in Figure 14 10 Associated with each outbound message register in a partition is a Switch Partition Message Control SWPxMSGCTL 3 0 register The register SWPxMSGCTLy corresp...

Page 266: ...age Status INMSGSTSx bit is set in the Message Status MSGSTS register Once a transferred value is accepted the inbound message register becomes full and remains full until the corresponding INTMSGSTSx...

Page 267: ...onds to device 0 func tion 4 The tag field is set to 0x0 In addition the BUSY bit in the PTCSTS register is set to indicate a punch through configuration transaction is in progress 4 Wait for the oper...

Page 268: ...ntelligent device uses a PES32NT24xG2 NT port to connect to the PCI Express switch Prior to initiating communication the CPU located in the intelligent device programs the PES32NT24xG2 NT port that fa...

Page 269: ...r DMA function e g BAR 0 aperture An MSI generated by the NT endpoint never multicasted Software must never configure the address of an MSI generated by the NT function to fall within an enabled multi...

Page 270: ...parallel with checking the ECRC if it exists of the received TLP The existence of an ECRC in the received TLP is indicated by the TD bit in the TLP header The NT function only checks and logs ECRC err...

Page 271: ...ct ACS Peer to Peer Completion Redirect ACS Direct Translated Peer to Peer ACS is programmed via the ACS Capability Structure in the NT function s configuration space The NT function supports ACS chec...

Page 272: ...er Request Redirect in the NT function This commands the NT function to re direct upstream i e transmit on the upstream link all requests that it issues which would have otherwise been logically route...

Page 273: ...CI Express Base Specification The error checking and handling described here is performed by each PES32NT24xG2 NT function In cases where the error condition propagates among multiple NT functions e g...

Page 274: ...fic These errors are described in the error handling section for the PCI to PCI bridge function Refer to section Physical Layer Errors on page 10 11 Data Link Layer Errors All data link layer errors a...

Page 275: ...ite request ECRC check fail ure2 2 7 1 No N A always non advisory Affected packet s ECRC is artifi cially corrupted as described in section ECRC Support on page 14 22 The TLP is forwarded across the N...

Page 276: ...set Completion with CA status received4 6 2 3 2 5 N A N A always non advisory Reception of a completions with CA status is handled as any other received completion In addition the Received Target Abo...

Page 277: ...list of link states in which the link is considered down e g L2 L3 Ready Refer to section Lookup Table Address Translation on page 14 5 and section Request ID Translation on page 14 11 n a Requester...

Page 278: ...LP on the port s link Conditions Handled as UC Description PCI Express Base Specification Section Non function specific unexpected completion Port receives a completion TLP that is not claimed by any...

Page 279: ...is only a sample configuration chosen to illustrate the concepts described in this section These concepts are applicable to all other possible multi partition configurations allowed by the PES32NT24xG...

Page 280: ...path will detect the error condition In other cases the first function in the TLP s logical path that detects an error will log the error appropri ately and allow the TLP to continue in its path As a...

Page 281: ...e func tion determines the request is unsupported the TLP is consumed by this function and is handled as a UR error Else the TLP is consumed and processed normally by the function or forwarded across...

Page 282: ...to PCI bridge function in the PES32NT24xG2 downstream switch port in the second partition Figure 14 15 Unsupported Request Example 2 When the downstream switch port s PCI to PCI bridge function in Pa...

Page 283: ...r The function that claims the TLP in the port that receives the poisoned TLP from the link logs the error in its AER Capability Structure and handles it appropriately A PCI to PCI bridge function tha...

Page 284: ...3 Upstream PCI to PCI Bridge Partition 1 Refer to row corresponding to Poisoned TLP received error in Table 10 9 Note that the bridge only logs parity error recep tion in the SECSTS register as it did...

Page 285: ...P a PCI to PCI bridge function may log a poisoned TLP error and forward the TLP to the next function in its logical route This next function may detect an unsupported request UR error on the TLP and h...

Page 286: ...s upstream port see section Transaction Layer Errors on page 10 13 Upstream PCI to PCI Bridge Partition 1 Refer to row corresponding to Poisoned TLP received error in Table 10 9 Note that the bridge o...

Page 287: ...egisters AERHL 1 4 DW in the switch have RWL type such that they may be modified by software to emulate the capturing of the TLP s header Error Emulation Usage and Limitations The following are some u...

Page 288: ...slated by the NT function must not map into a multicast BAR aperture in the destination partition The PCI Express Base Specification mandates that a requester not issue memory requests whose address l...

Page 289: ...s operation BAR 0 has an associated BAR Setup register BARSETUP0 The BAR setup register allows the BAR to be enabled and configured e g prefetchable memory 32 bit system memory or 64 bit system memory...

Page 290: ...y associated with any port and memory in another partition via an NT endpoint between two memory regions associated with another partition via an NT endpoint from any memory region to multiple memory...

Page 291: ...e at a time blocks of data are transferred as described in tbd Source addressing refers to the process of reading data from source memory while destination addressing refers to the process of writing...

Page 292: ...stride loop SSDIST Source Stride Distance Stride distance in bytes two s complement repre sentation of a positive or negative number Destination Addressing Parameters DADDR Destination Address Starti...

Page 293: ...ure 15 4 until the byte count is exhausted All stride counts i e SSCOUNT and DSCOUNT are set to one to indicate one iteration through the outer loop Since strides are not used all stride distances SSD...

Page 294: ...ield in the Data Transfer DMA Descriptor may cause the DMA to issue a single or multiple read operations to transfer the desired data For the example above if MRRS is set to 1 byte then the DMA would...

Page 295: ...g successful completion or error The Next Lower NEXTL and Next Upper NEXTU fields together form a 64 bit address that indi cates the address of a next descriptor in a descriptor list A value of zero i...

Page 296: ...processing the operation asso ciated with this descriptor 0x0 Unprocessed descriptor 0x1 Descriptor processing completed normally i e finished 0x2 Reserved 0x3 Descriptor processing completed due to a...

Page 297: ...ansfer descriptor is shown in Figure 15 9 and the fields are described in Table 15 5 Following the PCI convention the format is shown in little endian RRU 1 16 Request Rate Update When this bit is set...

Page 298: ...to setting the next descriptor address fields NEXTL and NEXTU to zero Refer to section DMA Descriptor Processing on page 15 15 for details DTC 0 10 8 Destination Traffic Class This field specifies the...

Page 299: ...his field indicates that the DMA controller has finished processing the operation asso ciated with this descriptor 0x0 Unprocessed descriptor 0x1 Descriptor processing completed normally i e finished...

Page 300: ...register of the PCI func tion with which the DMA channel is associated No error check is performed by the DMA channel and failure to follow this requirement produces undefined results In response to a...

Page 301: ...vice associated with the DMA transfer The format of an immediate data transfer descriptor is shown in Figure 15 10 and the fields are described in Table 15 6 Following the PCI convention the format is...

Page 302: ...eserved DTYPE 0 31 29 Descriptor Type This field encodes the type of descriptor and must be set to 0x2 in immediate data transfer DMA descriptors 0x0 Reserved 0x1 Data transfer DMA descriptor 0x2 Imme...

Page 303: ...DMACxCTL register when the DMA channel is idle As a side effect of writing a non zero value to the DMA Channel Descriptor Pointer Low DMACx DPTRL register Initiation of a DMA descriptor processing as...

Page 304: ...register Descriptor Chaining Without descriptor chaining a DMA channel halts descriptor processing when it reaches the last descriptor in a descriptor list i e one with the NEXTL and NEXTH fields set...

Page 305: ...ing to the DMACxNDPTRL register may be disabled by setting the Disable DMACxNDPTRL Descriptor Processing Initiation DISANDPTRL bit in the DMA Channel Configuration DMAxCFG register Execution of a desc...

Page 306: ...completions or completion time outs for all outstanding memory read requests Received completions are discarded i e the completions are not converted to memory write requests The DMACxDPTRL H register...

Page 307: ...ve approach to performing dynamic appending of descriptors to a descriptor list The mechanism described in this section is only applicable for dynamic appending of descriptor lists located below 4 GB...

Page 308: ...s described below are only applicable when the Enable Relaxed Ordering ENO bit in the DMA function s PCI Express Device Control PCIEDCTL register is set When this bit is cleared the DMA function does...

Page 309: ...sed to generate an interrupt in the DMA func tion with which the channel is associated Associated with each bit in the DMACxSTS register is a corresponding bit in the DMACxMSK register When a bit in t...

Page 310: ...ests when needed While this provides the highest level of performance it can also lead to congestion in the PCI Express topology and tax memory bandwidth To support background DMA operations i e ones...

Page 311: ...on transparent multicast When this occurs the posted TLP emitted by the DMA function is trans ferred to the upstream port s link i e the port where the DMA function resides as well as multicasted to t...

Page 312: ...ny port of the switch partition in which the DMA resides In addition an MSI generated by the DMA may be transmitted to a device i e link partner associated with any port of another switch partition by...

Page 313: ...in the DMA transfer Access Control Services ACS Support The DMA function supports the following ACS checks1 ACS Peer to Peer2 Request Redirect ACS Peer to Peer Completion Redirect ACS is programmed vi...

Page 314: ...of a ACS Peer to Peer Request Redirect The green lines mark the requests intended route and the orange lines the request s re directed route do to ACS Note that all peer to peer requests that the DMA...

Page 315: ...ing is not performed by the DMA function when it does not receive the TLP from the upstream port s link In this case the ECRC error checking and logging is done by the function that received the TLP f...

Page 316: ...es where a PCI Express error can be correlated to the operation of a DMA channel e g a completion timeout when a DMA channel reads a descriptor or when a PCI Express error causes one or all DMA channe...

Page 317: ...non function specific These errors are described in the error handling section for the PCI to PCI bridge function Refer to section Data Link Layer Errors on page 10 12 Transaction Layer Errors Table 1...

Page 318: ...ured as non fatal in the AERUESV register Yes See section Poisoned TLP Reception on page 15 32 Detected Parity Error bit PCISTS DPE is set Master Data Parity Error Detected bit PCISTS MDPED is set if...

Page 319: ...quest 2 3 1 Not applicable The DMA function never issues completions with Completer Abort status Unexpected completion received 2 3 2 Yes if a function claims the TLP Else No Advisory when the cor res...

Page 320: ...e The reception of any other type of poisoned TLP is handled as an unsupported request or unex pected completion ECRC Errors Refer to section ECRC Support on page 15 27 for details on ECRC support in...

Page 321: ...same completion timeout value If a DMA channel fails to receive all completions associated with a read request then this results in a completion time out error When a completion timeout associated wit...

Page 322: ...ones is recorded The following non function specific errors require that the offending TLP s header be logged in the DMA function s AER capability structure Reception of a TLP with ECRC error on the u...

Page 323: ...n t occur simultaneously The prioritization of errors shown in Table 15 13 determines the error that is logged and reported when multiple errors are detected simultaneously for the received TLP Higher...

Page 324: ...ion address memory writes to update memory before the same source address is read by the DMA channel TLP Received by DMA Function Receiver Overflow Error ECRC Error Handle per DMA Transaction Layer Er...

Page 325: ...d to all partitions not masked by the Switch Event Partition Mask SEPMSK register Associated with each of these events are further status and mask registers that provide fine grain status and masking...

Page 326: ...e P2PINTSTS or NTINTSTS register In addition it is recom mended that a switch manager device in charge of configuring the event signaling mechanism also be signaled of the occurrence of the event e g...

Page 327: ...tus bit is set in the SEFRSTSTS register the Fundamental Reset FRST status bit is set in the Switch Event Status SESTS register Hot Reset A hot reset event occurs within a partition when a partition h...

Page 328: ...MSK register When an unmasked status bit is set in the SEGSIGSTS register the Global Signal GSIGNAL status bit is set in the Switch Event Status SESTS register Figure 16 2 shows the global signaling m...

Page 329: ...global address space see Chapter 19 Port AER Errors It is possible to signal the occurrence of an AER error in any port as a switch event Each port contains an internal non software visible Port AER S...

Page 330: ...IDT Switch Events PES32NT24xG2 User Manual 16 6 January 30 2013 Notes...

Page 331: ...ection describes the PES32NT24xG2 transparent multicast Transparent multicast adheres to the Multicast functionality described in PCI Express Base Specification 2 1 Multicast operation is contingent u...

Page 332: ...ast TLPs The primary determinant of whether or not a memory write or address routed message TLP is a multicast TLP is its address and the address associated with multicast address regions A multicast...

Page 333: ...ition INDEXPOS field in the Multicast Base Address Low MCBARL register The size of each multi cast group region is equal to 2INDEXPOS The starting address of the region associated multicast group zero...

Page 334: ...e multicast group ID associated with a received multicast TLP is set in the ingress port then the multicast TLP is treated as a blocked multicast TLP The block all bits are contained in the ingress po...

Page 335: ...lticast TLP then the TLP is silently discarded This is not an error Note This section described multicast TLP routing from a functional perspective to aid in under standing This functional definition...

Page 336: ...osses partitions via the non transparent bridge NTB must not fall into a multicast window in the destination partition The NT translation in the NT function must be programmed to prevent this scenario...

Page 337: ...rformed at each egress port These tasks are described in the following sub sections Prior to this NT multicast configura tion is described Figure 17 3 Transparent and Non Transparent Multicast NT Mult...

Page 338: ...bed in section Multicast TLP Determination on page 17 1 except for the following requirements An NT multicast address region must not overlap a non multicast NT address region That is the NT multicast...

Page 339: ...T Multicast is only supported for multicast group IDs 0 1 2 and 3 Each NT Multicast Group x Port Association register corresponds to a multicast group ID e g NTMCG 0 PA corresponds to group 0 NTMCG 1...

Page 340: ...associated with the corresponding set of NT multicast overlay registers The Partition PART field in the NTMCOVRxC register selects the partition on which the NT multi cast must be received i e the sou...

Page 341: ...led i e either requester ID overlay or address overlay then the following actions are performed The ECRC of the original multicast TLP is checked while simultaneously the ECRC for the new modified TLP...

Page 342: ...IDT Multicast PES32NT24xG2 User Manual 17 12 January 30 2013 Notes...

Page 343: ...pt The TMPSENSOR bit in the P2PINTSTS register of the PCI to PCI bridge function is set when an enabled temperature sensor alarm is set When unmasked this bit causes the upstream PCI to PCI bridge fun...

Page 344: ...IDT Temperature Sensor PES32NT24xG2 User Manual 18 2 January 30 2013 Notes...

Page 345: ...the switch There is a 4 KB region for the configuration registers of each DMA function in the switch In addition there is one 8 KB region for switch configuration and status registers Base Address Ad...

Page 346: ...B000 Reserved 0x1C000 Port 14 PCI to PCI Bridge Registers 0x1D000 Reserved 0x1E000 Port 15 PCI to PCI Bridge Registers 0x1F000 Reserved 0x20000 Port 16 PCI to PCI Bridge Registers 0x21000 Port 16 NT E...

Page 347: ...Associated with each port is a bit in the Port PORT field of the Global Address Space Access Protection GASAPROT register When a bit in this field is set access to the global address space using the...

Page 348: ...ge function configuration space contains standard1 registers and capabilities defined for PCI Express as well as proprietary registers associated with proprietary port specific features section PCI to...

Page 349: ...2 returns a value of zero Writes to an address not defined in Table 19 2 completes successfully but modifies no data and has no other effect 0x000 PCI Configuration Space 64 Dwords 0x100 Advanced Erro...

Page 350: ...scription of the configuration register space behavior of a port in unattached mode Cfg Offset Size Register Mnemonic Register Definition US DS 0x000 Word VID VID Vendor Identification Register 0x000...

Page 351: ...0x04C DWord PCIELCAP PCIELCAP PCI Express Link Capabilities 0x04C on page 20 18 0x050 Word PCIELCTL PCIELCTL PCI Express Link Control 0x050 on page 20 21 0x052 Word PCIELSTS PCIELSTS PCI Express Link...

Page 352: ...ask 0x114 on page 20 48 0x118 DWord AERCTL AERCTL AER Capabilities and Control 0x118 on page 20 50 0x11C DWord AERHL1DW AERHL1DW AER Header Log 1st Doubleword 0x11C on page 20 50 0x120 DWord AERHL2DW...

Page 353: ...that the ACS Extended Capability structure is not applicable and must not be linked when the port operates in upstream switch port mode since the upstream port only has one function in this mode 0x32...

Page 354: ...0 0x330 ACS Extended Capability1 1 The ACS capability structure must not be linked when the upstream port operates in upstream switch port mode as ACS is only applicable for multi function port modes...

Page 355: ...port s operating mode For port operating modes in which the PCI to PCI bridge function is not present in the port the proprietary port registers are only accessible via the switch s global address spa...

Page 356: ...n Port Control Status Reserved 0x400 0x480 0xFFF 0xD90 Power Management Internal Error Reporting 0x500 0xE00 Control Status Registers Physical Layer Registers Global Address AER Error Emulation 0x880...

Page 357: ...page 21 20 0x4A4 DWord P2PIERRORMSK1 P2PIERRORMSK1 PCI to PCI Bridge Internal Error Reporting Mask 1 0x4A4 on page 21 25 0x510 DWord SERDESCFG SERDESCFG SerDes Configuration 0x510 on page 21 28 0x51C...

Page 358: ...39 0x914 DWord NTMCOVR1BARL NTMCOVR 3 0 BARL NT Multicast Overlay x Base Address Low on page 21 40 0x918 DWord NTMCOVR1BARH NTMCOVR 3 0 BARH NT Multicast Overlay x Base Address High on page 21 40 0x91...

Page 359: ...ing mode via the global address space access registers i e GASAADDR and GASADATA via the SMBus slave interface or via serial EEPROM Restrictions apply when using the GASAADDR and GASADATA registers Re...

Page 360: ...oint s configuration space contains the Extended Configuration Space Access Address and Data registers ECFGADDR and ECFGDATA Refer to the definition of these registers for further details 0x000 PCI Co...

Page 361: ...figuration space Cfg Offset Size Register Mnemonic Register Definition F0 F1 0x000 Word VID VID Vendor Identification 0x000 on page 22 1 0x002 Word DID DID Device Identification 0x002 on page 22 1 0x0...

Page 362: ...AP PCI Power Management Capabilities 0x0C0 on page 22 28 0x0C4 DWord PMCSR PMCSR PCI Power Management Control and Status 0x0C4 on page 22 28 0x0D0 DWord MSICAP MSICAP Message Signaled Interrupt Capabi...

Page 363: ...rd ACSECAPH ACSECAPH ACS Extended Capability Header 0x320 on page 22 48 0x324 Word ACSCAP ACSCAP ACS Capability 0x324 on page 22 48 0x326 Word ACSCTL ACSCTL ACS Control 0x326 on page 22 49 0x330 DWord...

Page 364: ...on page 22 65 0x454 DWord INMSGSRC1 INMSGSRC 3 0 Inbound Message Source 3 0 0x450 45C on page 22 65 0x458 DWord INMSGSRC2 INMSGSRC 3 0 Inbound Message Source 3 0 0x450 45C on page 22 65 0x45C DWord I...

Page 365: ...DR NT Mapping Table Address 0x4D0 on page 22 85 0x4D4 DWord NTMTBLSTS NTMTBLSTS NT Mapping Table Status 0x4D4 on page 22 86 0x4D8 DWord NTMTBLDATA NTMTBLDATA NT Mapping Table Data 0x4D8 on page 22 86...

Page 366: ...he ACS Extended Capability structure is not applicable and must never be linked ACS is not applicable to single function endpoints 0x608 DWord NTMCG2PA NTMCG 3 0 PA NT Multicast Group x Port Associati...

Page 367: ...ting mode via the global address space access registers i e GASAADDR and GASADATA located in each switch function via the SMBus slave interface or via serial EEPROM Restrictions apply when using the G...

Page 368: ...ss Capabilities List PCI Express Capability Structure 0x040 0x0C0 PCI Power Management Capability Structure 0x0C0 0x0D0 Message Signaled Interrupt Capability Structure 0x0D0 0x0 PCI Express Extended C...

Page 369: ...he NT endpoint s configuration space contains the Extended Configuration Space Access Address and Data registers ECFGADDR and ECFGDATA Refer to the definition of these registers for further details Th...

Page 370: ...028 on page 23 7 0x02C Word SUBVID SUBVID Subsystem Vendor ID Pointer 0x02C on page 23 7 0x02E Word SUBID SUBID Subsystem ID Pointer 0x02E on page 23 7 0x030 Word EROMBASE EROMBASE Expansion ROM Base...

Page 371: ...10C on page 23 31 0x110 DWord AERCES AERCES AER Correctable Error Status 0x110 on page 23 32 0x114 DWord AERCEM AERCEM AER Correctable Error Mask 0x114 on page 23 34 0x118 DWord AERCTL AERCTL AER Cont...

Page 372: ...nnel Next Descriptor Pointer High 0x534 634 on page 23 59 0x600 DWord DMAC1CTL DMAC 1 0 CTL DMA Channel Control 0x500 600 on page 23 50 0x604 DWord DMAC1CFG DMAC 1 0 CFG DMA Channel Configuration 0x50...

Page 373: ...ss space Offset addresses for these registers are shown in Table 19 11 Registers in this address range are referenced as REGNAME where REGNAME represents the register name in Table 19 11 Reading from...

Page 374: ...witch Partition Port 0x0500 0x1100 Configuration Registers Failover Capability GPIO Hot Plug SMBus 0x0C3C 0x0C00 GPE Control Registers 0x0700 Reserved Signals Registers Global Doorbell Registers 0x0E0...

Page 375: ...itch Partition x Failover Control on page 24 9 0x0140 DWord SWPART2CTL SWPART 7 0 CTL Switch Partition x Control on page 24 7 0x0144 DWord SWPART2STS SWPART 7 0 STS Switch Partition x Status on page 2...

Page 376: ...Word SWPORT5FCTL SWPORT 23 0 FCTL Switch Port x Failover Control on page 24 12 0x02C0 DWord SWPORT6CTL SWPORT 23 0 CTL Switch Port x Control on page 24 9 0x02C4 DWord SWPORT6STS SWPORT 23 0 STS Switch...

Page 377: ...DWord SWPORT17FCTL SWPORT 23 0 FCTL Switch Port x Failover Control on page 24 12 0x0440 DWord SWPORT18CTL SWPORT 23 0 CTL Switch Port x Control on page 24 9 0x0444 DWord SWPORT18STS SWPORT 23 0 STS S...

Page 378: ...4 15 0x0720 DWord NTMTBLPROT4 NTMTBLPROT 7 0 Partition x NT Mapping Table Protection on page 24 15 0x0724 DWord NTMTBLPROT5 NTMTBLPROT 7 0 Partition x NT Mapping Table Protection on page 24 15 0x0728...

Page 379: ...LMSK17 GODBELLMSK 31 0 NT Global Outbound Doorbell Mask 31 0 on page 24 25 0x0D48 DWord GODBELLMSK18 GODBELLMSK 31 0 NT Global Outbound Doorbell Mask 31 0 on page 24 25 0x0D4C DWord GODBELLMSK19 GODBE...

Page 380: ...ELLMSK 31 0 NT Global Inbound Doorbell Mask 31 0 on page 24 26 0x0DD8 DWord GIDBELLMSK22 GIDBELLMSK 31 0 NT Global Inbound Doorbell Mask 31 0 on page 24 26 0x0DDC DWord GIDBELLMSK23 GIDBELLMSK 31 0 NT...

Page 381: ...P 7 0 MSGCTL 3 0 Switch Partition x Message Control 3 0 on page 24 26 0x0E64 DWord SWP1MSGCTL3 SWP 7 0 MSGCTL 3 0 Switch Partition x Message Control 3 0 on page 24 26 0x0E68 DWord SWP2MSGCTL3 SWP 7 0...

Page 382: ...XLCTL0 S 7 0 TXLCTL0 SerDes x Transmitter Lane Control 0 on page 24 28 0x10E8 DWord S7TXLCTL1 S 7 0 TXLCTL1 SerDes x Transmitter Lane Control 1 on page 24 30 0x10F0 DWord S7RXEQLCTL S 7 0 RXEQLCTL Ser...

Page 383: ...24 45 0x11D8 DWord TMPSTS TMPSTS Temperature Sensor Status 0x11D8 on page 24 46 0x11DC DWord TMPALARM TMPALARM Temperature Sensor Alarm 0x11DC on page 24 47 0x11E0 DWord TMPADJ TMPADJ Temperature Sens...

Page 384: ...IDT Register Organization PES32NT24xG2 User Manual 19 40 January 30 2013...

Page 385: ...Register 0x002 Bit Field Field Name Type Default Value Description 15 0 VID RO 0x111D Vendor Identification This field contains the 16 bit vendor ID value assigned to IDT See section Vendor ID on page...

Page 386: ...ported Request UR completion This bit does not affect completions in either direction or the forwarding of non memory or I O requests 0x0 disable Disable request forwarding 0x1 enable Enable request f...

Page 387: ...bit For downstream switch ports this bit is set if an interrupt has been asserted by the corresponding port s hot plug controller 4 CAPL RO 0x1 Capabilities List This bit is hardwired to one to indic...

Page 388: ...xpress specification a completer is a component that terminates a request A request can be non posted e g memory read or posted e g memory write In the case of a non posted request the completer also...

Page 389: ...Type Default Value Description 7 0 PLTIMER RO 0x00 Primary Latency Timer Not applicable Bit Field Field Name Type Default Value Description 7 0 HDR RO See Description Header Type This field indicates...

Page 390: ...which the primary interface of the bridge is con nected This field has no functional effect within the switch but is implemented as a read write register for software compati bility Bit Field Field Na...

Page 391: ...ult Value Description 0 IOCAP RO 0x1 I O Capability Indicates if the bridge supports 16 bit or 32 bit I O address ing This bit always reflects the value of the IOCAP field in the IOBASE register 3 1 R...

Page 392: ...PCI Express specification a completer is a component that terminates a request A request can be non posted e g memory read or posted e g memory write In the case of a non posted request the completer...

Page 393: ...elow the primary interface of the bridge PMBASEU specifies the remaining bits Bit Field Field Name Type Default Value Description 0 PMCAP RO 0x1 Prefetchable Memory Capability Indicates if the bridge...

Page 394: ...e Description 15 0 IOBASEU RW 0xFFFF I O Address Base Upper This field specifies the upper 16 bits of IOBASE When the IOCAP field in the IOBASE register is cleared this field becomes read only with a...

Page 395: ...d by downstream switch ports Bit Field Field Name Type Default Value Description 7 0 INTRPIN RWL 0x0 SWSticky Interrupt Pin Interrupt pin or legacy interrupt messages are not used by the PCI to PCI br...

Page 396: ...0x0 ISA Enable This bit controls the routing of ISA I O transactions 0 disable Forward downstream all I O addresses in the address range defined by the I O base and I O limit registers 1 enable Forwar...

Page 397: ...t capability structure The default value of this register depends on the port s operating mode See section PCI to PCI Bridge Capability Structures on page 19 9 for details Note that this field is MSWS...

Page 398: ...tag identifier The value is hardwired to 0x0 to indicate that no function number bits are used for phan tom functions 5 ETAG RWL 0x1 SWSticky Extended Tag Field Support This field indicates the maxim...

Page 399: ...he value of this field is set by a Set_Slot_Power_Limit Message and is only applicable for an upstream port 1 A port in unattached mode does not modify this field as a result of receiving a Set_Slot_P...

Page 400: ...his field should be set to a value less than that advertised by the Maximum Payload Size Supported MPAYLOAD field in the PCI Express Device Capabilities PCIEDCAP register Setting this field to a value...

Page 401: ...ng is enabled or not 1 NFED RW1C 0x0 Non Fatal Error Detected This bit indicates the status of correctable errors detected by this function Errors are logged in this register regardless of whether err...

Page 402: ...d is automatically set by the hardware as described in section Port Maximum Link Width on page 7 1 0 reserved 1 x1 x1 link width 2 x2 x2 link width 4 x4 x4 link width 8 x8 x8 link width 12 x12 x12 lin...

Page 403: ...the removal of reference clocks 19 SDERR RWL Upstream Port 0x0 Downstream Switch Port 0x1 MSWSticky Surprise Down Error Reporting Downstream switch ports support surprise down error reporting This fi...

Page 404: ...MSWSticky Therefore if this field is modified by software its value will be preserved regardless of any port operating mode change 23 22 Reserved RO 0x0 Reserved field 31 24 PORTNUM RO Port 0 0x0 Port...

Page 405: ...Disable When set in a downstream switch port this bit disables the link Writes to this bit are immediately reflected in the value of the bit regardless of the actual link state This bit is not applic...

Page 406: ...n any of the port s functions 8 CLKPWRMGT RO 0x0 Enable Clock Power Management The switch does not support this feature 9 HAWD RO 0x0 Hardware Autonomous Width Disable Switch ports do not have a hardw...

Page 407: ...es in a multi function mode the above rules are based on the MAXLNKWDTH field for function 0 of the port Note that software must ensure that all functions of the port have identical MAXLNKWDTH field v...

Page 408: ...other reason The physical layer has autonomously changed link speed or width to attempt to correct unreliable link operation either through an LTSSM time out or a higher level process The physical lay...

Page 409: ...f zero when the SLOT bit in the PCIECAP register is cleared 4 PWRIP RWL 0x0 SWSticky Power Indicator Present This bit is set when an Power Indicator is implemented for the port This bit is read only a...

Page 410: ...nterlock Present This bit is set if an electromechanical interlock is imple mented on the chassis for this slot This bit is read only and has a value of zero when the SLOT bit in the PCIECAP register...

Page 411: ...he corresponding field in the PCIESCTLIV register Once this bit is modified the PCIESCTLIV register has no effect on this register until a subsequent partition fundamental reset occurs 2 MRLSCE RW HWI...

Page 412: ...e initial value of this field after a partition fundamental reset is equal to the value of the corresponding field in the PCIESCTLIV register Once this bit is modified the PCIESCTLIV register has no e...

Page 413: ...CAP regis ter When the corresponding capability is enabled the initial value of this field after a partition fundamental reset is equal to the value of the corresponding field in the PCIESCTLIV regist...

Page 414: ...gle command even if it affects more than one field in that register This command completed bit is not set until processing of all actions asso ciated with all fields in the PCIESCTL register have com...

Page 415: ...applicable 4 CTDS RO 0x0 Completion Timeout Disable Supported Not applicable 5 ARIFS Upstre am Port RO Down stream Switch Port RWL Upstream Port 0x0 Down stream Switch Port 0x1 MSWSticky ARI Forwardin...

Page 416: ...Not applicable 5 ARIFEN Upstre am Port RO Down stream Switch Port RW 0x0 ARI Forwarding Enable When set the downstream switch port disables its tradi tional Device Number field being zero enforcement...

Page 417: ...s used to set the target compliance mode speed when soft ware is using the ECOMP bit in this register to force a link into compliance mode The switch supports 2 5 GT s and 5 0 GT s operation Set ting...

Page 418: ...is field is reset to 0x0 on entry to the LTSSM Polling Configuration substate 0x0 Normal operating range 0x1 900 mV for full swing and 500 mV for low swing 0x2 700 mV for full swing and 400 mV for low...

Page 419: ...ticky Compliance De emphasis This bit selects the de emphasis value in the Polling Com pliance state when this state was entered as a result of set ting the Enter Compliance ECOMP bit in this register...

Page 420: ...VER RO 0x3 Power Management Capability Version Complies with version the PCI Bus Power Management Interface Specification Revision 1 2 19 PMECLK RO 0x0 PME Clock Does not apply to PCI Express 20 Rese...

Page 421: ...PME Enable When this bit is set PME message generation is enabled for the function If a hot plug wake up event is desired when exiting the D3cold state then this bit should be set during serial EEPRO...

Page 422: ...e Capability Structures on page 19 9 for details Note that this field is MSWSticky Therefore if this field is modified by software its value will be preserved regardless of any port operating mode cha...

Page 423: ...on Interrupts on page 10 4 for restrictions on the programming of this field Bit Field Field Name Type Default Value Description 15 0 MDATA RW 0x0 Message Data This field contains the lower 16 bits of...

Page 424: ...7 2 2 of the PCI Express Base Specifi cation The value of this register must not be programmed to point to the address offset of this register i e 0xF8 or the ECF GDATA register i e 0xFC Violation of...

Page 425: ...me Type Default Value Description 15 0 CAPID RO 0x1 Capability ID The value of 0x1 indicates an advanced error reporting capability structure 19 16 CAPVER RO 0x2 Capability Version The value of 0x2 in...

Page 426: ...for ACS violations For this exception case the error is an ACS violation error and is not logged as a completer abort error 16 UECOMP RW1C 0x0 Sticky Unexpected Completion Status This bit is set when...

Page 427: ...esponding event is not logged in the advanced capability structure the First Error Pointer field FEPTR in the AERCTL register is not updated and an error is not reported to the root complex This bit d...

Page 428: ...8 MALFORMED RW 0x0 Sticky Malformed TLP Mask When this bit is set the corresponding bit in the AERUES register is masked When a bit is masked in the AERUES register the corresponding event is not logg...

Page 429: ...nal Error Reporting Control IER RORCTL register this field becomes read only with a value of zero 23 MCBLKTLP RW 0x0 Sticky MC Blocked TLP Mask When this bit is set the corresponding bit in the AERUES...

Page 430: ...d the event is reported as a non fatal error 17 RCVOVR RW 0x1 Sticky Receiver Overflow Severity This bit controls the severity of the reported error If this bit is set the event is reported as a fatal...

Page 431: ...cOp Egress Blocked Severity Not applicable 25 TLPPBE RO 0x0 TLP Prefix Blocked Error Severity Not applicable 31 26 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 0...

Page 432: ...Reporting Enable IERROREN bit is cleared in the Internal Error Reporting Control IER RORCTL register this field becomes read only with a value of zero 31 16 Reserved RO 0x0 Reserved field Bit Field F...

Page 433: ...to the root complex This bit does not affect the state of the corresponding bit in the AERCES register 14 CIE RW 0x1 Sticky Correctable Internal Error Mask When this bit is set the corresponding bit...

Page 434: ...tion is enabled for the function 7 ECRCCC RWL 0x1 SWSticky ECRC Check Capable This bit indicates if the function is capable of checking ECRC 8 ECRCCE RW 0x0 Sticky ECRC Check Enable When this bit is s...

Page 435: ...value of 0x3 indicates a device serial number capability structure 19 16 CAPVER RO 0x1 Capability Version The value of 0x1 indicates compatibility with version 1 of the specification 31 20 NXTPTR RWL...

Page 436: ...identically in all functions that imple ment this capability 1 Reading from a reserved address returns and undefined value Writes to a reserved address complete success fully but produce undefined be...

Page 437: ...eld Bit Field Field Name Type Default Value Description 7 0 VCARBCAP RO 0x0 VC Arbitration Capability Not applicable only the default VC0 is implemented 23 8 Reserved RO 0x0 Reserved field 31 24 VCATB...

Page 438: ...O 0x0 Maximum Time Slots Since this VC does not support time based WRR this field is not valid 23 Reserved RO 0x0 Reserved field 31 24 PATBLOFF RO 0x0 Port Arbitration Table Offset Device ports only s...

Page 439: ...Negotiation Pending This bit is not applicable for VC0 and is therefore hardwired to 0x0 31 18 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 15 0 CAPID RO 0xD Cap...

Page 440: ...ulti function upstream port peer to peer refers to transfers among functions in the port In an upstream port this field can only be set to 0x1 when the port s operating mode is a multi function mode i...

Page 441: ...tch ports in the same partition For a multi function upstream port peer to peer refers to transfers among functions in the port This bit is ignored if the ACS Translation Blocking B bit is set to 0x1...

Page 442: ...field becomes read only zero when the corre sponding bit in the ACSCAP register is cleared 2 R RW 0x0 ACS P2P Request Redirect Enable When set this function performs ACS Peer to Peer Request Redirect...

Page 443: ...ess Control Vector This field is used to configure ACS peer to peer egress control The value in this field is only valid when ACS peer to peer egress control is enabled in the ACSCTL register Each bit...

Page 444: ...erminates the list The default value of this register depends on the port s operating mode See section PCI to PCI Bridge Capability Structures on page 19 9 for details Note that this field is MSWStick...

Page 445: ...arti tion associated with this port This field must be set identically in all port functions in the partition associated with this port Bit Field Field Name Type Default Value Description 5 0 INDEXPOS...

Page 446: ...bit 1 corresponds to multicast group 1 and so on When a bit is set in this field for an enabled multicast group multicast TLPs associated with that multicast group that reach the virtual PCI bus of t...

Page 447: ...this field corresponds to one of the upper 32 multicast groups e g bit 0 corresponds to multicast group 32 bit 1 corresponds to multicast group 33 and so on When a bit is set in this field for an enab...

Page 448: ...om for warding untranslated multicast TLPs associated with that multicast group received on that port This is an ingress port function performed on received TLPs The value of bits greater than NUMGROU...

Page 449: ...rietary Weighted Round Robin WRR Arbitration on page 4 8 for further details 15 1 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 2 0 Reserved RO 0x0 Reserved field...

Page 450: ...ports 31 8 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 2 0 Reserved RO 0x0 Reserved field 3 SEVENT RW 0x1 Switch Event When this bit is set in an upstream port t...

Page 451: ...ing set in the Global Signal GSIGNAL field in the Switch Event Global Signal Status SEGSIGSTS register This field always returns a value of zero when read This bit is read only with a value of zero in...

Page 452: ...in the internal non software visible PAERSTS register is masked 11 Reserved RO 0x0 Reserved field 12 MCBLKTLP RW 0x0 Sticky MC Blocked TLP Mask When this bit is set the corresponding bit in the intern...

Page 453: ...ental reset Refer to the description of the corresponding field in the PCIESCTL register for further details 1 PFDE RW 0x0 SWSticky Power Fault Detected Enable This field contains the initial value of...

Page 454: ...the PCI Express Slot Control PCIESCTL register when the corresponding slot or hot plug capability is enabled The intent of this field is to allow the initial value of the cor responding field in the P...

Page 455: ...Layer Link Active State Change Enable This field contains the initial value of the corresponding field in the PCI Express Slot Control PCIESCTL register when the corresponding slot or hot plug capabi...

Page 456: ...single bit ECC error is detected and corrected in the IFB control RAM 10 IFBCTLDBE RW1C 0x0 SWSticky IFB Control Double Bit Error This bit is set when a double bit ECC error is detected in the IFB co...

Page 457: ...hat contain a DMA func tion When not applicable this bit is hardwired to 0x0 24 DIFBDATDBE RW1C 0x0 SWSticky DMA IFB Data Double Bit Error This bit is set when a double bit ECC error is detected in th...

Page 458: ...ERMSK register 3 P3AER RW1C 0x0 SWSticky Port 3 AER Error This bit is at the time that port 3 detects an AER error in one of its functions and the error is not masked by the corre sponding Port AER Ma...

Page 459: ...an AER error in one of its functions and the error is not masked by the cor responding Port AER Mask PAERMSK register 15 P15AER RW1C 0x0 SWSticky Port 15 AER Error This bit is at the time that port 1...

Page 460: ...cleared the error is reported as an correctable internal error 1 IFBNPTLPTO RW 0x0 SWSticky IFB Non Posted TLP Time Out This bit controls how an error of the corresponding type is reported When this b...

Page 461: ...ed as an uncorrectable internal error When this bit is cleared the error is reported as an correctable internal error 11 EFBDATSBE RW 0x0 SWSticky EFB Data Single Bit Error This bit controls how an er...

Page 462: ...cable for ports that contain a DMA func tion When not applicable this bit remains read write but has no effect 20 DIFBNPTLPTO RW 0x0 SWSticky DMA IFB Non Posted TLP Time Out This bit controls how an e...

Page 463: ...r ports that contain a DMA func tion When not applicable this bit remains read write but has no effect 27 DEFBDATSBE RW 0x0 SWSticky DMA EFB Data Single Bit Error This bit controls how an error of the...

Page 464: ...s cleared the error is reported as an correctable internal error 4 P4AER RW 0x0 SWSticky Port 4 AER Error This bit controls how an error of the corresponding type is reported When this bit is set the...

Page 465: ...ted as an uncorrectable internal error When this bit is cleared the error is reported as an correctable internal error 14 P14AER RW 0x0 SWSticky Port 14 AER Error This bit controls how an error of the...

Page 466: ...type is reported When this bit is set the error is reported as an uncorrectable internal error When this bit is cleared the error is reported as an correctable internal error 22 P22AER RW 0x0 SWStick...

Page 467: ...15 E2EPE RW 0x0 End to End Data Path Parity Error This bit always returns a value of zero when read 16 ULD RW 0x0 Unreliable Link Detected This bit always returns a value of zero when read 17 RBCTLSB...

Page 468: ...Error This bit always returns a value of zero when read This bit is only applicable for ports that contain a DMA func tion 27 DEFBDATSBE RW 0x0 DMA EFB Data Single Bit Error This bit always returns a...

Page 469: ...ity Structure of the PCI to PCI bridge function This bit does not affect the state of the cor responding bit in the IERRORSTS0 1 register 6 EFBCPTLPTO RW 0x0 SWSticky EFB Completion TLP Time Out When...

Page 470: ...PCI to PCI bridge function This bit does not affect the state of the cor responding bit in the IERRORSTS0 1 register 14 EFBCTLDBE RW 0x0 SWSticky EFB Control Double Bit Error When this bit is set the...

Page 471: ...it remains read write but has no effect 21 DIFBCPTLPTO RW 0x1 SWSticky DMA IFB Completion TLP Time Out When this bit is set the corresponding error bit in the IERRORSTS0 1 register is masked from repo...

Page 472: ...ister is masked from reporting an inter nal error to the AER Capability Structure of the PCI to PCI bridge function This bit does not affect the state of the cor responding bit in the IERRORSTS0 1 reg...

Page 473: ...egister is masked from reporting an inter nal error to the AER Capability Structure of the PCI to PCI bridge function This bit does not affect the state of the cor responding bit in the IERRORSTS0 1 r...

Page 474: ...PCI to PCI bridge function This bit does not affect the state of the cor responding bit in the IERRORSTS0 1 register 12 P12AER RW 0x1 SWSticky Port 12 AER Error When this bit is set the corresponding...

Page 475: ...ge function This bit does not affect the state of the cor responding bit in the IERRORSTS0 1 register 20 P20AER RW 0x1 SWSticky Port 20 AER Error When this bit is set the corresponding error bit in th...

Page 476: ...W 0x0 SWSticky Receiver Detect Override Each bit in this register corresponds to a lane associated with this port Setting this bit causes the lane associated with this bit to indicate that a receiver...

Page 477: ...when the corresponding link receiver is unable to compensate for clock variance between link partners and has dropped one or more bytes A bit can only be set when the LTSSM is in the L0 state 31 24 R...

Page 478: ...RW 0x0 SWSticky Disable Link Width Upconfiguration Capability When this bit is set the port does not advertise support for link width upconfiguration in the training sets it issues dur ing the Configu...

Page 479: ...or NT and DMA function mode Modification of this field causes all functions of the port to operate using this bus number e g completions generated by the function s use this bus number in the complet...

Page 480: ...Request DLLP will be treated as a new request 31 17 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 0 EN RW 0x0 SWSticky Enable When this bit is set request metering...

Page 481: ...fixed point 0 13 11 number i e an unsigned num ber with 13 integer bits and 11 fractional bits The value in this field represents an unsigned number with 13 integer bits and 3 fractional bits The lea...

Page 482: ...ial value of this field is 0xFF in Port 4 and 0x0 in all other ports In Port 4 this field must never be set to 0x0 Refer to section Cut Through Routing on page 4 9 for details 15 8 P5IC RW See Descrip...

Page 483: ...ing to port 10 The initial value of this field is 0xFF in Port 10 and 0x0 in all other ports In Port 10 this field must never be set to 0x0 Refer to section Cut Through Routing on page 4 9 for details...

Page 484: ...l value of this field is 0xFF in Port 16 and 0x0 in all other ports In Port 16 this field must never be set to 0x0 Refer to section Cut Through Routing on page 4 9 for details 15 8 P17IC RW See Descri...

Page 485: ...s 0xFF in Port 22 and 0x0 in all other ports In Port 22 this field must never be set to 0x0 Refer to section Cut Through Routing on page 4 9 for details 31 24 P23IC RW See Description SWSticky Port 23...

Page 486: ...rent Multicast Operation on page 17 6 for details 1 NTMCAOE RW 0x0 NT Multicast Address Overlay Enable This bit when set enables NT multicast NT Multicast address overlay When cleared NT multicast add...

Page 487: ...st Group i e bit 0 corresponds to NT Multicast Group 0 bit 1 corre sponds to NT Multicast Group 1 etc When an NT multicast TLP is received on a group whose corresponding bit is set in this field and a...

Page 488: ...ails on programming this field Bit Field Field Name Type Default Value Description 31 0 MCBARH RW 0x0 Multicast Overlay BAR High This field specifies the upper 32 bits i e bits 32 through 63 of the NT...

Page 489: ...sponding error bit to get set in the PCI to PCI Bridge function s AERUES reg ister This bit always returns 0x0 when read 20 UR RW 0x0 SWSticky UR Trigger Writing a one to this bit causes the correspon...

Page 490: ...ses the corresponding error bit to get set in the PCI to PCI Bridge function s AERCES reg ister This bit always returns 0x0 when read 5 1 Reserved RO 0x0 Reserved field 6 BADTLP RW 0x0 SWSticky Bad TL...

Page 491: ...ddress of the GASAADDR or GASA DATA register in this or any other function 2 The value of this register must not be programmed to point to the address of the Extended Configuration Address and Data re...

Page 492: ...IDT Proprietary Port Specific Registers PES32NT24xG2 User Manual 21 44 January 30 2013 Notes...

Page 493: ...signed by IDT to this device See section Device ID on page 1 1 Bit Field Field Name Type Default Value Description 0 IOAE RW 0x0 I O Access Enable When this bit is cleared the function does not respon...

Page 494: ...D field in the PCISTS register When this bit is cleared poisoned TLPs are not reported as master data parity errors in the PCISTS regis ter 7 ADSTEP RO 0x0 Address Data Stepping Not applicable 8 SERRE...

Page 495: ...eter abort status 12 RTAS RW1C 0x0 Received Target Abort This bit is set when the NT function receives a completion with Completer Abort completion status 0x0 noerror no error 0x1 error This bit is se...

Page 496: ...BASE RO 0x06 Base Class Code This value indicates that the device is a bridge Bit Field Field Name Type Default Value Description 7 0 CLS RW 0x00 Cache Line Size This field has no effect on the functi...

Page 497: ...this field is always zero 0x0 addr32 32 bit addressing Located in lower 4 GB address space 0x1 reserved reserved 0x2 addr64 64 bit addressing 0x3 reserved reserved 3 PREF RO 0x0 Prefetchable If the M...

Page 498: ...ned by the TYPE field in the BARSETUP1 register 0x0 addr32 32 bit addressing Located in lower 4 GB address space 0x1 reserved reserved 0x2 reserved reserved 0x3 reserved reserved 3 PREF RO 0x0 Prefetc...

Page 499: ...r64 64 bit addressing 0x3 reserved reserved 3 PREF RO 0x0 Prefetchable If the MEMSI field selects memory this field indicates if the memory is prefetchable When the MEMSI field indicates I O space thi...

Page 500: ...ned by the TYPE field in the BARSETUP3 register 0x0 addr32 32 bit addressing Located in lower 4 GB address space 0x1 reserved reserved 0x2 reserved reserved 0x3 reserved reserved 3 PREF RO 0x0 Prefetc...

Page 501: ...r64 64 bit addressing 0x3 reserved reserved 3 PREF RO 0x0 Prefetchable If the MEMSI field selects memory this field indicates if the memory is prefetchable When the MEMSI field indicates I O space thi...

Page 502: ...ned by the TYPE field in the BARSETUP5 register 0x0 addr32 32 bit addressing Located in lower 4 GB address space 0x1 reserved reserved 0x2 reserved reserved 0x3 reserved reserved 3 PREF RO 0x0 Prefetc...

Page 503: ...ng PCI configuration space e g via EEPROM Refer to the PCI 3 0 specification Section 6 2 4 for further information Bit Field Field Name Type Default Value Description 15 0 SUBID RWL 0x0 SWSticky Subsy...

Page 504: ...x0 SWSticky Interrupt Pin The value in this register indicates the INTx message e g INTA INTB etc used by this function This field has RWL type to allow system designers to change the INTx generated b...

Page 505: ...tes that the function is a PCI Express End point function 24 SLOT RO 0x0 Slot Implemented Not applicable 29 25 IMN RO 0x0 Interrupt Message Number The function is allocated only one MSI Therefore this...

Page 506: ...dicates the acceptable total latency that an end point can withstand due to transition from the L1 state to the L0 state The value defaults to 0x7 indicating that this function places no limit on the...

Page 507: ...et Capability This function does not support function level reset There fore this field is hardwired to 0x0 31 29 Reserved RO 0x0 Reserved field 1 NOTE Set_Slot_Power_Limit messages received by a port...

Page 508: ...Field Enable When this bit is set Request TLPs generated by the func tion use an 8 bit tag i e allows up to 256 outstanding requests Else Request TLPs generated by the function use a 5 bit tag i e all...

Page 509: ...CED RW1C 0x0 Correctable Error Detected This bit indicates the status of correctable errors detected by this function Errors are logged in this register regardless of whether error reporting is enabl...

Page 510: ...s automatically set by the hardware as described in section Port Maximum Link Width on page 7 1 0 reserved 1 x1 x1 link width 2 x2 x2 link width 4 x4 x4 link width 8 x8 x8 link width 12 x12 x12 link w...

Page 511: ...clock via the CLKREQ mechanism The switch does not support the removal of reference clocks 19 SDERR RO 0x0 Surprise Down Error Reporting Not applicable to upstream ports 20 DLLLA RO 0x0 Data Link Lay...

Page 512: ...as no functional effect on the behavior of the NTB 4 LDIS RO 0x0 Link Disable Not applicable 5 LRET RWL 0x0 Link Retrain This field is only applicable for port operating modes in which the NT function...

Page 513: ...ended Sync When set this bit forces transmission of additional ordered sets when exiting the L0s state and when in the recovery state When a port operates in a multi function mode the effect of this b...

Page 514: ...re that all functions of the port have identical MAXLNKWDTH field values 10 Reserved RO 0x0 Reserved field 11 LTRAIN RO 0x0 Link Training Not applicable 12 SCLK RWL HWINIT SWSticky Slot Clock Configur...

Page 515: ...Not supported 19 14 Reserved RO 0x0 Reserved field 20 EFMTFS RO 0x0 Extended Fmt Field Supported The switch does not support the 3 bit definition of the FMT field in TLPs 21 E2ETPS RO 0x0 End to End...

Page 516: ...tion timeout it is recommended that software set this bit 5 ARIFEN RO 0x0 ARI Forwarding Enable Not applicable 6 ATOPRE RO 0x0 AtomicOp Requester Enable Not supported 7 ATOPEB RO 0x0 AtomicOp Egress B...

Page 517: ...ftware is permitted to force a link into compliance mode at the speed indicated by the TLS field by setting this bit in both components on a link and then initiat ing a hot reset on the link 5 HASD RO...

Page 518: ...hen this field is set to Normal Operating Range the SerDes transmitter drive level is selected via the SerDes Transmitter Control registers S x TXLCTL0 and S x TXLCTL1 Refer to section SerDes Transmit...

Page 519: ...0 of the port When applicable This bit selects the de emphasis value in the Polling Com pliance state when this state was entered as a result of set ting the Enter Compliance ECOMP bit in this registe...

Page 520: ...face Specification Revision 1 2 19 PMECLK RO 0x0 PME Clock Does not apply to PCI Express 20 Reserved RO 0x0 Reserved field 21 DEVSP RWL 0x0 SWSticky Device Specific Initialization The value of zero in...

Page 521: ...s not implemented 15 PMES RW1C 0x0 Sticky PME Status Since this function never generates a PME this bit will never be set 21 16 Reserved RO 0x0 Reserved field 22 B2B3 RO 0x0 B2 B3 Support Does not app...

Page 522: ...ss This field specifies the lower portion of the DWORD address of the MSI memory write transaction Refer to section Interrupts on page 14 20 for restrictions on the programming of this field Bit Field...

Page 523: ...description MSWSticky Next Pointer This field contains a pointer to the next capability structure The default value of this register depends on the port s operating mode See section NT Function Capab...

Page 524: ...I Express Base Specification Rev 2 1 The following restrictions apply when programming this reg ister 1 The value of this register must not be programmed to point to the address offset of this registe...

Page 525: ...he specification 3 1 Reserved RO 0x0 Reserved field 4 DLPERR RW1C 0x0 Sticky Data Link Protocol Error Status This bit is set when a data link layer protocol error is detected 5 SDOENERR RO 0x0 Surpris...

Page 526: ...IERROREN bit is cleared in the Internal Error Reporting Control IER RORCTL register this field becomes read only with a value of zero The IERRORCTL register is a proprietary register located in the co...

Page 527: ...Error Mask Not applicable 14 COMPTO RW 0x0 Sticky Completion Timeout Mask This function does not track non posted requests it trans mits i e requests that crossed the NTB Therefore this bit has no ef...

Page 528: ...s not reported to the root complex This bit does not affect the state of the corresponding bit in the AERUES register 20 UR RW 0x0 Sticky UR Mask When this bit is set the corresponding bit in the AERU...

Page 529: ...PCI Bridge Function on page 19 11 for details 23 MCBLKTLP RW 0x0 Sticky MC Blocked TLP Mask Not applicable 24 ATOPEB RO 0x0 AtomicOp Egress Blocked Mask Not applicable 25 TLPPBE RO 0x0 TLP Prefix Blo...

Page 530: ...If this bit is set the event is reported as a fatal error When this bit is cleared the event is reported as an uncorrectable error 20 UR RW 0x0 Sticky UR Severity This bit controls the severity of th...

Page 531: ...link be retrained 11 9 Reserved RO 0x0 Reserved field 12 RPLYTO RW1C 0x0 Sticky Replay Timer timeout Status This bit is set when the replay timer in the data link layer times out 13 ADVISORYNF RW1C 0x...

Page 532: ...to section Proprietary Port Specific Regis ters in the PCI to PCI Bridge Function on page 19 11 for details 31 16 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 0 R...

Page 533: ...the corresponding bit in the AERCES register is masked When a bit is masked in the AERCES register the corresponding event is not reported to the root complex This bit does not affect the state of the...

Page 534: ...Field Name Type Default Value Description 4 0 FEPTR RO 0x0 Sticky First Error Pointer This field contains a pointer to the bit in the AERUES regis ter that resulted in the first reported error This f...

Page 535: ...icky Header Log This field contains the 2nd doubleword of the TLP header that resulted in the first reported uncorrectable error Bit Field Field Name Type Default Value Description 31 0 HL RWL 0x0 Sti...

Page 536: ...ort s operating mode See section NT Function Capability Struc tures on page 19 22 for details Note that this field is MSWSticky Therefore if this field is modified by software its value will be preser...

Page 537: ...tion 2 0 EVCCNT RO 0x0 Extended VC Count A value 0x0 indicates that only the default VC VC0 is implemented 3 Reserved RO 0x0 Reserved field 6 4 LPEVCCNT RO 0x0 Low Priority Extended VC Count Not appli...

Page 538: ...ARBSEL RW 0x0 VC Arbitration Select Not applicable only the default VC0 is implemented This field has RW type for compliance with the PCI Express Base Specification 15 4 Reserved RO 0x0 Reserved field...

Page 539: ...e Not applicable 19 17 PARBSEL RO 0x0 SWSticky Port Arbitration Select Not applicable 23 20 Reserved RO 0x0 Reserved field 26 24 VCID RO 0x0 VC ID This field assigns a VC ID to the VC resource For VC0...

Page 540: ...icable to multi function upstream ports 1 B RO 0x0 ACS Translation Blocking Not applicable to multi function upstream ports 2 R RWL 0x0 SWSticky ACS P2P Request Redirect If set indicates that this fun...

Page 541: ...Enable Not applicable to multi function upstream ports 2 R RW 0x0 ACS P2P Request Redirect Enable When set this function performs ACS Peer to Peer Request Redirect for function to function transfers...

Page 542: ...modified by software its value will be preserved regardless of any port operating mode change Bit Field Field Name Type Default Value Description 5 0 MAXGROUP RWL 0x3 SWSticky Max Multicast Groups Th...

Page 543: ...is port 11 6 Reserved RO 0x0 Reserved field 31 12 MCBARL RW 0x0 Multicast BAR Low This field specifies the lower 20 bits i e bits 12 through 31 of the multicast BAR The behavior is undefined if bits i...

Page 544: ...mum of 4 groups 31 4 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 31 0 MCRCV RO 0x0 Multicast Receive Not applicable as the NT function supports a maximum of 4 gr...

Page 545: ...ugh the NT endpoint 0x0 enable ID protection check enable 0x1 disable ID protection check disable 1 CPEN RW 0x0 Completion Enable When this bit is cleared the NT endpoint does not emit completion TLPs...

Page 546: ...ted to the partition with which the NT endpoint is associ ated i e when the corresponding event bit in the SESTS register transitions from 0x0 to 0x1 Refer to section Switch Events on page 16 1 for de...

Page 547: ...ponding bit in the NTINTSTS register is masked from generating an interrupt 2 Reserved RO 0x0 Reserved field 3 SEVENT RW 0x1 Switch Event When this bit is set the corresponding bit in the NTINTSTS reg...

Page 548: ...LP Time Out When this bit is set the corresponding error bit in the IERRORSTS0 1 register is masked from reporting an inter nal error to the AER Capability Structure of the NT function This bit does n...

Page 549: ...ure of the NT function This bit does not affect the state of the corresponding bit in the IERRORSTS0 1 register 10 IFBCTLDBE RW 0x0 SWSticky IFB Control Double Bit Error When this bit is set the corre...

Page 550: ...AER Capability Structure of the NT function This bit does not affect the state of the corresponding bit in the IERRORSTS0 1 register 18 RBCTLDBE RW 0x0 SWSticky Replay Buffer Control Double Bit Error...

Page 551: ...error bit in the IERRORSTS0 1 register is masked from reporting an inter nal error to the AER Capability Structure of the NT function This bit does not affect the state of the corresponding bit in th...

Page 552: ...ved but remains read write in the hard ware Modifying this field has no effect other than changing the value of the field 31 DE2EPE RW 0x1 SWSticky DMA End to End Data Path Parity Error When this bit...

Page 553: ...cture of the NT function This bit does not affect the state of the corresponding bit in the IERRORSTS0 1 register 6 P6AER RW 0x1 SWSticky Port 6 AER Error When this bit is set the corresponding error...

Page 554: ...cture of the NT function This bit does not affect the state of the corresponding bit in the IERRORSTS0 1 register 14 P14AER RW 0x1 SWSticky Port 14 AER Error When this bit is set the corresponding err...

Page 555: ...ction This bit does not affect the state of the corresponding bit in the IERRORSTS0 1 register 21 P21AER RW 0x1 SWSticky Port 21 AER Error When this bit is set the corresponding error bit in the IERRO...

Page 556: ...urns 0x0 Refer to section Doorbell Registers on page 14 16 for details Bit Field Field Name Type Default Value Description 31 0 INDBELLSTS RW1C 0x0 Inbound Doorbell Status Each bit in this field corre...

Page 557: ...INMSG RO 0x0 Inbound Message This read only field contains the value written by an agent to an Outbound Message OUTMSG register that is mapped to this register See section Message Registers on page 1...

Page 558: ...Registers on page 14 17 for a description of the message registers 18 INMSGSTS2 RW1C 0x0 Inbound Message 2 Status This bit is set when the INMSG2 register is updated While this bit is set the INMSG2...

Page 559: ...TS3 RW 0x0 Inbound Message 3 Mask When this bit is set assertion of the corresponding bit in the MSGSTS register is masked from generating an interrupt 31 20 Reserved RO 0x0 Reserved field Bit Field F...

Page 560: ...he smallest memory size that may be requested by PCI Express is 128 i e SIZE equal to 7 and the largest is 231 bytes for 32 bit address space and 263 bytes for 64 bit address space Setting the SIZE fi...

Page 561: ...the upper bits are provided by the BARLIMIT1 regis ter When the MODE field in the BARSETUP0 register is set to 0x1 i e the BAR is mapped to configuration space this field must be set to a value equal...

Page 562: ...rned in the MEMSI field of the corresponding BAR When the MEMSI field in BARSETUP0 is set to memory space i e zero and the TYPE field is set to 64 bit addressing BAR1 takes on the function of the uppe...

Page 563: ...by the BADDR field in the corre sponding BAR is equal to 2SIZE Bits in the BAR BADDR field correspond to PCI Express address bits For example bit 0 or the BAR BADDR field corresponds to PCI Express Ad...

Page 564: ...d and returns a zero when read i e configuration values in this register are ignored and all fields of the BAR take on a value of zero When the MEMSI field in BARSETUP0 is set to memory space i e zero...

Page 565: ...WSticky Translated Base Address When the BAR is configured for direct address translation this field specifies the translated base address The translated base address is 64 bits This field contains bi...

Page 566: ...g BAR BADDR field to take on a read only zero value that effectively disables the BAR The smallest memory size that may be requested by PCI Express is 128 i e SIZE equal to 7 and the largest is 231 by...

Page 567: ...red to operate as an address win dow this field specifies the limit address associated with the BAR When the BAR is configured to operate as a 64 bit address window this field acts as the lower bits o...

Page 568: ...2 In this mode this field remains RW but has no functional effect on the operation of the device 0x0 memory memory space 0x1 reserved 2 1 TYPE RW 0x0 SWSticky Address Select This field determines the...

Page 569: ...and cannot be modified Setting the SIZE field to a value less than four results in all bits in the corresponding BAR BADDR field to take on a read only zero value that effectively disables the BAR The...

Page 570: ...bits of the BADDR field in BAR2 In this mode this field remains RW but has no functional effect on the operation of the device 0x0 disabled disabled 0x1 enabled enabled Bit Field Field Name Type Defau...

Page 571: ...dress The translated base address is 64 bits This field contains bits 32 through 63 of the translated base address The cor responding BAR lower translated base address register contains the lower bits...

Page 572: ...and 263 bytes for 64 bit address space When the BAR is configured to operate as an address win dow with lookup table address translation valid values for the SIZE field are 14 through 37 values greate...

Page 573: ...s configured to operate as a 64 bit address window this field acts as the lower bits of the LADDR field while the upper bits are provided by the BARLIMIT5 regis ter Bit Field Field Name Type Default V...

Page 574: ...rned in the MEMSI field of the corresponding BAR When the MEMSI field in BARSETUP4 is set to memory space i e zero and the TYPE field is set to 64 bit addressing BAR5 takes on the function of the uppe...

Page 575: ...by the BADDR field in the corre sponding BAR is equal to 2SIZE Bits in the BAR BADDR field correspond to PCI Express address bits For example bit 0 or the BAR BADDR field corresponds to PCI Express Ad...

Page 576: ...and returns a zero when read i e configuration values in this register are ignored and all fields of the BAR take on a value of zero When the MEMSI field in BARSETUP4 is set to memory space i e zero...

Page 577: ...ays zero Refer to section Non Transparent Operation Restrictions on page 14 40 for restrictions on programming this field Bit Field Field Name Type Default Value Description 31 0 TADDR RW 0x0 SWSticky...

Page 578: ...apping table entry specified by the partition NT Mapping table address in the NTMTBLADDR register Writing to this field updates the FUNC field of the NT Mapping table entry specified by the partition...

Page 579: ...NT function Refer to section Address Type Processing on page 14 15 30 CNS RW SWSticky Completion No Snoop Processing This field specifies the processing performed on the no snoop attribute in the head...

Page 580: ...configured for 12 entry lookup table and the BAR field in this register selects BAR 4 the INDEX field must only be set to values 0 to 11 7 5 Reserved RO 0x0 Reserved field 10 8 BAR RW 0x0 SWSticky Lo...

Page 581: ...This field contains the partition field of the lookup table entry selected by the BAR and INDEX fields of the Lookup Table Offset LUTOFFSET register The value read from this field corresponds to the v...

Page 582: ...ed TLP Trigger Writing a one to this bit causes the corresponding error bit to get set in the AERUES register This bit always returns 0x0 when read 19 ECRC RW 0x0 SWSticky ECRC Trigger Writing a one t...

Page 583: ...ERR RW 0x0 SWSticky Receiver Error Trigger Writing a one to this bit causes the corresponding error bit to get set in the AERCES register This bit always returns 0x0 when read 5 1 Reserved RO 0x0 Rese...

Page 584: ...Express Base Specifi cation in the punch through configuration request 11 8 EREG RW 0x0 Extended Register Number This field selects the extended configuration register num ber as defined by Section 7...

Page 585: ...nfiguration Data A write to this field will generate a configuration read or write transaction as selected by the OP field in the PTCCFG1 register on the NT endpoint s link The byte enables in the gen...

Page 586: ...rt Status This bit is set if the last punch through configuration trans action was aborted i e the STATUS field in this register is set to requester abort This bit will remain set until the next punch...

Page 587: ...ly the value of this register must not be programmed to point to the address of the Extended Configuration Address ECFGADDR or Extended Configuration Data registers ECFGDATA in this or any other funct...

Page 588: ...IDT NT Endpoint Registers PES32NT24xG2 User Manual 22 96 January 30 2013 Notes...

Page 589: ...device ID assigned by IDT to this device See section Device ID on page 1 1 Bit Field Field Name Type Default Value Description 0 IOAE RO 0x0 I O Access Enable The DMA function does not implement Base...

Page 590: ...trols the logging of poisoned TLPs in the Master Data Parity Error Detected MDPED field in the PCI Status PCISTS register When this bit is cleared poisoned TLPs are not reported as master data parity...

Page 591: ...ned request 10 9 DEVT RO 0x0 DEVSEL TIming Not applicable 11 STAS RO 0x0 Signaled Target Abort Not applicable since the DMA function never issues com pletions with completer abort status 12 RTAS RW1C...

Page 592: ...D on page 1 1 Bit Field Field Name Type Default Value Description 7 0 INTF RWL 0x00 SWSticky Interface No standard interface defined 15 8 SUB RWL 0x80 SWSticky Sub Class Code This value indicates that...

Page 593: ...Space Indicator This bit determines if the base address register maps into memory space or I O space This bit is always 0x0 since the DMA function does not sup port I O space 0x0 memory memory space 0...

Page 594: ...ates memory and the TYPE field indicates 64 bit addressing the upper bits of the address of the BADDR field are contained in the next consecutive odd numbered BAR i e BAR1 See the PCI and PCI Express...

Page 595: ...field identifies the vendor of the subsystem This field must be loaded with the subsystem vendor ID prior to system software accessing PCI configuration space e g via EEPROM Refer to the PCI 3 0 speci...

Page 596: ...ecture specific The function does not use the value in this register Bit Field Field Name Type Default Value Description 7 0 INTRPIN RWL 0x0 SWSticky Interrupt Pin The value in this register indicates...

Page 597: ...ility structure The default value of this register depends on the port s operating mode See section DMA Function Registers on page 19 23 for details Note that this field is MSWSticky Therefore if this...

Page 598: ...value is hardwired to 0x0 to indicate that no function number bits are used for phan tom functions 5 ETAG RWL 0x1 SWSticky Extended Tag Field Support This field indicates the maximum supported size o...

Page 599: ...e value of this field is set by a Set_Slot_Power_Limit Message received by the port 1 27 26 CSPLS RO 0x0 Captured Slot Power Limit Scale This field specifies the scale used for the Slot Power Limit Va...

Page 600: ...aximum Payload Size Supported MPAYLOAD field in the PCI Express Device Capabilities PCIEDCAP register Setting this field to a value larger than that adver tised in the MPAYLOAD field produces undefine...

Page 601: ...x0 Initiate Function Level Reset This function does not support function level reset There fore this field is hardwired to 0x0 Bit Field Field Name Type Default Value Description 0 CED RW1C 0x0 Correc...

Page 602: ...icky Maximum Link Width This field indicates the maximum link width of the given PCI Express link This field may be overridden to allow the link width to be forced to a smaller value When modifying th...

Page 603: ...l values in this field i e when the port operates in a multi function mode 17 15 L1EL RWL 0x2 SWSticky L1 Exit Latency This field indicates the L1 exit latency for the given PCI Express link Transitio...

Page 604: ...corresponds to disabled 0x0 disabled disabled 0x1 l0s L0s enable entry 0x2 l1 L1 enable entry 0x3 l0sl1 L0s and L1 enable entry Note that L0s enable entry corresponds to the transmitter entering L0s t...

Page 605: ...and L1 exit latencies do not change among common and non common clock configurations 7 ESYNC RW 0x0 Extended Sync When set this bit forces transmission of additional ordered sets when exiting the L0s...

Page 606: ...ns of the port have identical MAXLNKWDTH field values 10 Reserved RO 0x0 Reserved field 11 LTRAIN RO 0x0 Link Training Not applicable 12 SCLK RWL HWINIT SWSticky Slot Clock Configuration When set this...

Page 607: ...omicOp Completer Supported Not supported 8 ATOPC64S RO 0x0 64 bit AtomicOp Completer Supported Not supported 9 CASC128S RO 0x0 128 bit CAS Completer Supported Not supported 10 NROEP RO 0x1 No RO enabl...

Page 608: ...e start time for each request either on when this value was changed or on when each request was issued 4 CTD RW 0x0 Completion Timeout Disable When this bit is set completion timeout checking is dis a...

Page 609: ...RO 0x0 Enter Compliance Not applicable function 0 of the port controls this function ality 5 HASD RO 0x0 Hardware Autonomous Speed Disable Not applicable function 0 of the port controls this function...

Page 610: ...ky Next Pointer This field contains a pointer to the next capability structure The default value of this register depends on the port s operating mode See section DMA Function Registers on page 19 23...

Page 611: ...nfiguration context is preserved by the function when the device transitions from a D3hot to D0 power management state 0x0 reset State reset 0x1 preserved State preserved 7 4 Reserved RO 0x0 Reserved...

Page 612: ...ils Note that this field is MSWSticky Therefore if this field is modified by software its value will be preserved regardless of any port operating mode change 16 EN RW 0x0 Enable This bit enables MSI...

Page 613: ...ection Interrupts on page 15 24 for restrictions on the programming of this field Bit Field Field Name Type Default Value Description 15 0 MDATA RW 0x0 Message Data This field contains the lower 16 bi...

Page 614: ...n of this rule produces undefined results 31 12 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 31 0 DATA RW 0x0 Configuration Data A read from this field will retur...

Page 615: ...s Not applicable 11 6 Reserved RO 0x0 Reserved field 12 POISONED RW1C 0x0 Sticky Poisoned TLP Status This bit is set when a poisoned TLP is detected 13 FCPERR RO 0x0 Flow Control Protocol Error Status...

Page 616: ...ed TLP Status Not applicable the DMA function does not have a multicast capability structure 24 ATOPEB RO 0x0 AtomicOp Egress Blocked Status Not applicable 25 TLPPBE RO 0x0 TLP Prefix Blocked Error St...

Page 617: ...n this bit is set the corresponding bit in the AERUES register is masked When a bit is masked in the AERUES register the corresponding event is not logged in the AER Header Log registers the First Err...

Page 618: ...e AER Header Log registers the First Error Pointer field FEPTR in the AERCTL register is not updated and an error is not reported to the root complex This bit does not affect the state of the correspo...

Page 619: ...ut Severity This bit controls the severity of the reported error If this bit is set the event is reported as a fatal error When this bit is cleared the event is reported as an uncorrectable error 15 C...

Page 620: ...nly with a value of one The IERRORCTL register is a proprietary register located in the configuration space of the port s PCI to PCI bridge function Refer to section Proprietary Port Specific Regis te...

Page 621: ...CI to PCI Bridge Function on page 19 11 for details 15 HLO RW1C 0x0 Sticky Header Log Overflow Status This bit is set when an error that requires packet header logging occurs but the packet header can...

Page 622: ...the AERCES register the corresponding event is not reported to the root complex This bit does not affect the state of the corresponding bit in the AERCES register 8 RPLYROVR RW 0x0 Sticky Replay Numb...

Page 623: ...d in the AERCES register the corresponding event is not reported to the root complex This bit does not affect the state of the corresponding bit in the AERCES register When the Internal Error Reportin...

Page 624: ...witch ports do not support recording of multiple packet headers As a result this bit is hardwired to 0x0 31 11 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 31 0 H...

Page 625: ...ss Base Specification 31 20 NXTPTR RWL HWINIT See description MSWSticky Next Pointer This field contains a pointer to the next capability structure The default value of this register depends on the po...

Page 626: ...Enable Not applicable to multi function upstream ports 1 B RO 0x0 ACS Translation Blocking Enable Not applicable to multi function upstream ports 2 R RW 0x0 ACS P2P Request Redirect Enable When set th...

Page 627: ...decoding used when memory space is selected in the MEMSI field in this register 0x0 addr32 32 bit addressing Located in lower 4 GB address space 0x1 reserved reserved 0x2 addr64 64 bit addressing 0x3...

Page 628: ...s the corresponding error bit to get set in the PCI to PCI Bridge function s AERUES reg ister This bit always returns 0x0 when read 18 MALFORMED RW 0x0 SWSticky Malformed TLP Trigger Writing a one to...

Page 629: ...sponding error bit to get set in the PCI to PCI Bridge function s AERCES reg ister This bit always returns 0x0 when read 5 1 Reserved RO 0x0 Reserved field 6 BADTLP RW 0x0 SWSticky Bad TLP Trigger Wri...

Page 630: ...apability Structure of the DMA func tion This bit does not affect the state of the corresponding bit in the IERRORSTS0 1 register 2 IFBCPTLPTO RW 0x0 SWSticky IFB Completion TLP Time Out When this bit...

Page 631: ...e of the DMA func tion This bit does not affect the state of the corresponding bit in the IERRORSTS0 1 register 10 IFBCTLDBE RW 0x0 SWSticky IFB Control Double Bit Error When this bit is set the corre...

Page 632: ...his bit does not affect the state of the corresponding bit in the IERRORSTS0 1 register 18 RBCTLDBE RW 0x0 SWSticky Replay Buffer Control Double Bit Error When this bit is set the corresponding error...

Page 633: ...ster is masked from reporting an inter nal error to the AER Capability Structure of the DMA func tion This bit does not affect the state of the corresponding bit in the IERRORSTS0 1 register 27 DEFBDA...

Page 634: ...ister is masked from reporting an inter nal error to the AER Capability Structure of the DMA func tion This bit does not affect the state of the corresponding bit in the IERRORSTS0 1 register 4 P4AER...

Page 635: ...of the DMA func tion This bit does not affect the state of the corresponding bit in the IERRORSTS0 1 register 12 P12AER RW 0x1 SWSticky Port 12 AER Error When this bit is set the corresponding error...

Page 636: ...c tion This bit does not affect the state of the corresponding bit in the IERRORSTS0 1 register 20 P20AER RW 0x1 SWSticky Port 20 AER Error When this bit is set the corresponding error bit in the IERR...

Page 637: ...ubject to NT Multicast handling see section Non Trans parent Multicast Operation on page 17 6 When this bit is one a multicast TLP emitted by the DMA is transmitted on the upstream port s link only wh...

Page 638: ...of descriptor lists refer to section Dynamic Appending of Descriptor Lists on page 15 19 Writing a zero to this bit position has no effect on the opera tion of the DMA channel This bit is automaticall...

Page 639: ...tor 0x3 reserved Refer to section DMA Descriptor Processing on page 15 15 for details 6 ODRC RW 0x1 Outstanding Data Request Control This field controls the number of outstanding requests issued by th...

Page 640: ...to prefetch 0x0 disable Disable DMA descriptor prefetching 0x1 one Prefetch one DMA descriptor 0x2 Reserved 0x3 Reserved 31 18 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value D...

Page 641: ...egister is masked from generating an inter rupt 1 A RW 0x1 Abort When this bit is set the corresponding bit in the DMACxSTS register is masked from generating an inter rupt 2 E RW 0x1 Error When this...

Page 642: ...ved in response to a descriptor read Refer to section Completion with CA Status Received on page 15 34 for details 5 DSCCT RW1C 0x0 Descriptor Completion Time Out Error This bit is set when a completi...

Page 643: ...rom setting the Error E bit in the DMACxSTS register 2 DSCECRC RW 0x1 De featured This bit has no effect as the corresponding status bit in the DMAC 1 0 ERRSTS register is invalid 3 DSCUR RW 0x1 Descr...

Page 644: ...served RW 0x1 Reserved field 30 21 Reserved RO 0x0 Reserved field 31 ECRCE RW 0x0 ECRC Error When this bit is set the corresponding bit in the DMACx ERRSTS register is masked from setting the Error E...

Page 645: ...ies the DMA channel stride distance in bytes This value in this field is a signed number in two s complement notation The value in this field is modified by a stride control DMA descriptor The value i...

Page 646: ...tor pro cessing The value returned by this field when read represents the address of the currently active DMA descriptor The DMACxDPTRL and DMACxDPTRH together form a 64 bit address Bit Field Field Na...

Page 647: ...o this register Writing a zero to this field modifies the contents of the regis ter but does not automatically start DMA descriptor pro cessing The DMACxNDPTRL and DMACxNDPTRH together form a 64 bit a...

Page 648: ...ECFGDATA in this or any other function 3 The value of this register must not be programmed to point to the NT Mapping Table Address and Data NTMT BLADDR and NTMTBLDATA registers in any NT function Vi...

Page 649: ...s bit Writing a value of one to this bit produces unde fined results 3 REGUNLOCK RW 0x0 SWSticky Register Unlock When this bit is set the contents of registers and fields of type Read and Write when U...

Page 650: ...reset 9 RSTHALT RO HWINIT Reset Halt Boot configuration vector value sampled during a switch fundamental reset 13 10 Reserved RO 0x0 Reserved field 15 14 CLKMODE RO HWINIT Clock Mode Boot configuratio...

Page 651: ...4 and 5 Clocking Mode See P0CLKMODE description 7 6 P6CLKMODE RW 0x0 SWSticky Ports 6 and 7 Clocking Mode See P0CLKMODE description 9 8 P8CLKMODE RW 0x0 SWSticky Ports 8 to 11 Clocking Mode See P0CLK...

Page 652: ...or further details 31 5 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 4 0 STKCFG RW HWINIT SWSticky Stack Configuration This field selects the configuration of the...

Page 653: ...easing this value is discouraged except for the cases explicitly stated in this specification 31 16 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 15 0 POMCDELAY RW...

Page 654: ...k partner prior to the side effect Refer to section Configuration Register Side Effects on page 19 3 for details The default value corresponds to 1 millisecond Decreasing this delay is discouraged exc...

Page 655: ...n are dis abled As a result the DL_Down condition on the upstream port does not cause a hot reset on the upstream port i e the port s configuring space is not affected and the hot reset is not propaga...

Page 656: ...current state of the switch partition Due to the time it takes for a partition state change to com plete this value may be different than that in the STATE field in the SWPARTxCTL register 0x0 disable...

Page 657: ...itch port 0x2 upstream Upstream switch port 0x3 ntb NT function 0x4 upstream_ntb Upstream switch port with NT function 0x5 unattached Unattached 0x6 upstream_dma Upstream switch port with DMA function...

Page 658: ...ct This field selects the failover capability associated with the port 0x0 Failover Capability 0 0x1 Failover Capability 1 0x2 Failover Capability 2 0x3 Failover Capability 3 31 22 Reserved RO 0x0 Res...

Page 659: ...Disabled 0x1 downstream Downstream switch port 0x2 upstream Upstream switch port 0x3 ntb NT function 0x4 upstream_ntb Upstream switch port with NT function 0x5 unattached Unattached 0x6 upstream_dma...

Page 660: ...SWPART field of the SWPORTxCTL register 9 7 Reserved RO 0x0 Reserved field 14 10 PFDEVNUM RW 0x0 SWSticky Primary Failover Device Number This field specifies the primary failover device number On a p...

Page 661: ...dary to primary This field always returns a value of zero when read 1 FSIGEN RW 0x0 SWSticky Failover Signal Trigger Enable When this bit is set a failover is initiated when the state of the correspon...

Page 662: ...s or partitions are sensi tive to the failover capability the failover mode change completes immediately after the failover is triggered i e this bit is set immediately after the FMCI bit is set 31 3...

Page 663: ...nctions of the port 31 24 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 5 0 TBLBASE RW 0x0 SWSticky NT Mapping Table Base This field specifies the NT Mapping table...

Page 664: ...Status SEGSIGSTS register 7 6 Reserved RO 0x0 Reserved field 8 P0AER RW1C 0x0 SWSticky Port 0 AER Error This bit is set at the time that port 0 detects an AER error in one of its functions i e any bit...

Page 665: ...l non software visible PAERSTS register and the error is not masked by the corresponding Port AER Mask PAERMSK register 16 P8AER RW1C 0x0 SWSticky Port 8 AER Error This bit is set at the time that por...

Page 666: ...ernal non software visible PAERSTS register and the error is not masked by the corresponding Port AER Mask PAERMSK register 24 P16AER RW1C 0x0 SWSticky Port 16 AER Error This bit is set at the time th...

Page 667: ...rt 23 AER Error This bit is set at the time that port 23 detects an AER error in one of its functions i e any bit is set in the correspond ing internal non software visible PAERSTS register and the er...

Page 668: ...AER Error When this bit is set the corresponding bit in the SESTS register is masked from generating a switch event 16 P8AER RW 0x1 SWSticky Port 8 AER Error When this bit is set the corresponding bi...

Page 669: ...set the corresponding bit in the SESTS register is masked from generating a switch event 29 P21AER RW 0x1 SWSticky Port 21 AER Error When this bit is set the corresponding bit in the SESTS register is...

Page 670: ...eld Name Type Default Value Description 23 0 LINKUP RW 0xFF_FFFF SWSticky Link Up When a bit in this field is set the corresponding bit in the SELINKUPSTS register is masked from generating a switch e...

Page 671: ...it Field Field Name Type Default Value Description 7 0 FRST RW 0xFF SWSticky Partition Fundamental Reset When a bit in this field is set the corresponding bit in the SEFRSTSTS register is masked from...

Page 672: ...hen this bit is set the Failover Mode Change Initiated FMCI bit in the Failover Capability 3 Status FCAP3STS register is masked from generating a switch event 15 4 Reserved RO 0x0 Reserved field 16 FC...

Page 673: ...ld Name Type Default Value Description 7 0 GSIGNAL RW 0xFF SWSticky Global Signal When a bit in this field is set the corresponding bit in the SEGSIGSTS register is masked from generating a switch eve...

Page 674: ...d corresponds to a partition When a bit in this field is set the global doorbell corre sponding to this register is masked from affecting the state of the inbound doorbell in the partition associated...

Page 675: ...not affected by this field i e reading from a SerDes lane control register returns the last value written to that register regardless of the setting of this field Operating on a reserved lane results...

Page 676: ...l of the transmit driver de emphasis level in Gen 2 mode when the SDE field in the associated port s PCIELCTL2 register is set to 3 5dB de emphasis This field has no effect when the port operates in l...

Page 677: ...for the lane s selected by the Lane Select LANESEL 3 0 field in the SerDes Control S x CTL register This value is SWSticky for all lanes i e even those not selected by the LANESEL field in the S x CTL...

Page 678: ...when the port operates in low swing mode i e de emphasis is turned off in this mode This field controls the voltage level for the lane s selected by the Lane Select LANESEL 3 0 field in the SerDes Con...

Page 679: ...set to 6 0dB de emphasis The value of this field corresponds to the peak to peak differential voltage at the transmitter pins prior to de emphasis being applied This field controls the voltage level f...

Page 680: ...CTL register Refer to section Low Swing Transmitter Voltage Mode on page 8 12 for further details on programming this field 31 28 TDVL_LSG2 RW 0xC SWSticky Transmit Driver Voltage Level for Low Swing...

Page 681: ...x CTL register 5 3 RXEQB RW 0x7 SWSticky Receive Equalization Boost Reduces the low frequency gain of the equalizer Setting both RXEQZ and RXEQB to zero results in turning off the receiver equalizatio...

Page 682: ...elect See AFSEL0 field description in the GPIOAFSEL0 register 11 10 AFSEL5 RW 0x0 SWSticky GPIO Pin 5 Alternate Function Select See AFSEL0 field description in the GPIOAFSEL0 register 13 12 AFSEL6 RW...

Page 683: ...inverted in all ports 1 IPXPDN RW 0x0 SWSticky Invert Polarity of PxPDN When this bit is set the polarity of the PxPDN input is inverted in all ports 2 IPXPFN RW 0x0 SWSticky Invert Polarity of PxPFN...

Page 684: ...ent 11 MRLPWROFF RW 0x1 SWSticky MRL Automatic Power Off When this bit is set and the Manual Retention Latch Pres ent MRLP bit is set in the PCI Express Slot Capability PCIESCAP register then power to...

Page 685: ...to no delay The default value corresponds to 200 mS Bit Field Field Name Type Default Value Description 0 Reserved RO 0x0 Reserved field 7 1 SSMBADDR RO HWINIT Slave SMBus Address This field contains...

Page 686: ...l Reset this bit is set when serial EEPROM ini tialization completes or is aborted 25 NAERR RW1C 0x0 SWSticky No Acknowledge Error This bit is set if an unexpected NACK is observed during a master SMB...

Page 687: ...on the SSMBCLK and SSMBDAT signals that wait approximately 1uS before sampling or driving these signals This field allows the glitch counter time to be reduced or entirely removed In some systems this...

Page 688: ...ue Description 7 0 BYTE0 RO 0x0 Configuration Block Byte 0 This field contains byte 0 of the last serial EEPROM config uration block processed normally by the SMBus master interface Refer to section I...

Page 689: ...This bit is set when a serial EEPROM read or write opera tion is in progress 0x0 idle serial EEPROM interface idle 0x1 busy serial EEPROM interface operation in prog ress 25 DONE RW1C 0x0 SWSticky EEP...

Page 690: ...R RWL 0x0 SWSticky I O Expander 5 Address This field contains the SMBus address assigned to I O expander 5 on the master SMBus interface 16 Reserved RO 0x0 Reserved field 23 17 IOE6ADDR RWL 0x0 SWStic...

Page 691: ...WL 0x0 SWSticky I O Expander 13 Address This field contains the SMBus address assigned to I O expander 13 on the master SMBus interface 16 Reserved RO 0x0 Reserved field 23 17 IOE14ADDR RWL 0x0 SWStic...

Page 692: ...erved RO 0x0 Reserved field 15 9 IOE21ADDR RWL 0x0 SWSticky I O Expander 21 Address This field contains the SMBus address assigned to I O expander 21 on the master SMBus interface 31 16 Reserved RO 0x...

Page 693: ...ture in degrees Celsius i e an unsigned number with 7 integer bits and 1 fractional bit 23 16 HTH RW 0x0 SWSticky High Temperature Threshold This field contains the high temperature threshold The valu...

Page 694: ...l upstream port PCI to PCI bridge and NT functions respectively 30 Reserved RO 0x0 Reserved field 31 PDOWN RW 0x1 SWSticky Power Down When this bit is set the temperature sensor is powered down and th...

Page 695: ...d RO 0x0 Reserved field 15 8 LTEMP RW 0xFF SWSticky Low Temperature This field contains the lowest temperature recorded since the field was reset The value in the field represents a fixed point 0 7 1...

Page 696: ...This field is automatically cleared as a side effect of register being read The field may be set to any value to facilitate software testing by writing to this register 28 BHTH RW1C 0x0 SWSticky Below...

Page 697: ...ved field 14 12 DACOFFSET RW 0x0 SWSticky D to A Converter Offset Current source offset for D to A Converter DAC 15 Reserved RO 0x0 Reserved field 19 16 DACGAIN RW 0x0 SWSticky D to A Converter Gain C...

Page 698: ...justment 6 120 degree adjustment 30 28 Reserved RO 0x0 Reserved field 31 ADJDOWN RW 0x1 SWSticky Slope Adjustment Down If cleared slope adjustment values in these register repre sent positive adjustme...

Page 699: ...e system logic utilizes a 16 state TAP controller a six bit instruction register and five dedicated pins to perform a variety of functions The primary use of the JTAG TAP Controller state machine is t...

Page 700: ...active low Asynchronous reset for JTAG TAP controller internal pull up JTAG_TCK Input JTAG Clock Test logic clock JTAG_TMS and JTAG_TDI are sampled on the rising edge JTAG_TDO is output on the fallin...

Page 701: ...TP 1 0 O PE02RN 1 0 I O PE02RP 1 0 I PE02TN 1 0 O C PE02TP 1 0 O PE03RN 1 0 I O PE03RP 1 0 I PE03TN 1 0 O C PE03TP 1 0 O PE04RN 1 0 I O PE04RP 1 0 I PE04TN 1 0 O C PE04TP 1 0 O PE05RN 1 0 I O PE05RP 1...

Page 702: ...I PE12TN 0 O C PE12TP 0 O PE13RN 0 I O PE13RP 0 I PE13TN 0 O C PE13TP 0 O PE14RN 0 I O PE14RP 0 I PE14TN 0 O C PE14TP 0 O PE15RN 0 I O PE15RP 0 I PE15TN 0 O C PE15TP 0 O PE16RN 0 I O PE16RP 0 I PE16TN...

Page 703: ...P 0 O PE22RN 0 I O PE22RP 0 I PE22TN 0 O C PE22TP 0 O PE23RN 0 I O PE23RP 0 I PE23TN 0 O C PE23TP 0 O P 20 16 12 8 6 4 2 0 CLKN3 I P 20 16 12 8 6 4 2 0 CLKP3 I GCLKN 1 0 I GCLKP 1 0 I SMBus MSMBCLK I...

Page 704: ...CFG3 STK3CFG4 PERSTN I O RSTHALT I O SWMODE 3 0 I EJTAG JTAG JTAG_TCK I JTAG_TDI I JTAG_TDO O JTAG_TMS I JTAG_TRST_N I SerDes Reference Resistors REFRES00 I O REFRES01 I O REFRES02 I O REFRES03 I O RE...

Page 705: ...nding outputs or output enables Therefore the SAMPLE PRELOAD instruction must first be used to load suitable values into the boundary scan cells so that inappropriate values are not driven out onto th...

Page 706: ...gister allows an instruction to be shifted serially into the device at the rising edge of JTAG_TCK The instruction is then used to select the test to be performed or the test register to be accessed o...

Page 707: ...e put into BYPASS mode Instruction Definition Opcode EXTEST Mandatory instruction allowing the testing of board level interconnec tions Data is typically loaded onto the latched parallel outputs of th...

Page 708: ...e device contains a Device ID register it must also contain a BYPASS register The only difference is that the BYPASS register will not be the default register selected during the TAP controller reset...

Page 709: ...IR state After this instruction is asserted the width of the pulse is the amount of time for which the JTAG state machine is held in the Run Test Idle state If the Run Test Idle state is not entered...

Page 710: ...IDT JTAG Boundary Scan PES32NT24xG2 User Manual 25 12 January 30 2013 Notes...

Page 711: ...several related devices are used as examples however each example is also applicable to the PES32NT24xG2 Boot time Stack Reconfiguration Goal Reconfigure the stacks at boot time via serial EEPROM to...

Page 712: ...rt mode While the serial EEPROM loading executes the switch is kept in quasi reset mode see section Partition Resets on page 3 11 To meet PCI Express conventional reset requirements serial EEPROM conf...

Page 713: ...KMODE register to select local port clocking mode In response the switch automatically changes the port s clock mode using the sequence described in section Port Clocking Mode Selection on page 2 6 If...

Page 714: ...tion As dictated by the switch mode all ports and partitions are initially disabled To meet PCI Express conventional reset requirements serial EEPROM configuration completes within 1 second after the...

Page 715: ...n the Detect state until the reset is de asserted While the serial EEPROM loading executes the switch is kept in quasi reset mode see section Partition Resets on page 3 11 After EEPROM loading complet...

Page 716: ...switch partitions as described below and then proceeds to enumeration As indicated in section Partition Resets on page 3 11 the switch manager has 1 second to configure the switch after the deassertio...

Page 717: ...wnstream requires that the OMA field in the SWPORTxCTL register be set to Reset See section Port Operating Mode Change on page 5 13 Following the operating mode change each port s link will train with...

Page 718: ...root complex Port 16 x1 is configured in NT function mode and is connected to a switch manager The other ports x2 are downstream ports in their respective partitions and are connected to endpoint dev...

Page 719: ...by using the global signaling mechanism as follows RC0 writes a message to the P2PSDATA register in port 0 The message is a system specific message requesting I O resources The encoding of such messag...

Page 720: ...s a message to the switch manager by re configuring the global signaling mechanism such that it can send global signals to the switch manager device see description above The quiescing of traffic alth...

Page 721: ...nect Goal Describe the process of interconnecting loosely coupled multiprocessors using the switch s non trans parent bridges Assumptions The switch is configured as shown in Figure 26 7 The configura...

Page 722: ...ex in a partition enumerates the partition it will allocate 4 KB of non prefetchable memory space and assign it to BAR 0 in the NT function The driver associated with the NT function accesses the func...

Page 723: ...able protection is also enabled to prevent agent s in a partition from configuring the NT Mapping table inappropriately Specifically an agent in a partition is only allowed to program the NT Mapping t...

Page 724: ...nt device RC0 programs the NT Mapping table as follows Note The table entries programmed in the NT Mapping table need not be contiguous This completes the programming of the NT translation mechanism O...

Page 725: ...boots in switch mode Multi partition with Unattached ports Prior to serial EEPROM initialization the system is as shown in Figure 26 8 All ports are configured in unattached mode and all partitions ar...

Page 726: ...sts are sent from port 8 in switch 1 to port 8 in switch 2 via the cross link formed between these devices The punch through configuration requests target function 0 of the port 8 in switch 2 Specific...

Page 727: ...onfiguration sequence Using the same mechanism the serial EEPROM can access the GASADATA register in the port 8 of switch 2 By using the GASAADDR and GASADATA registers to access any register in switc...

Page 728: ...meet PCI Express conventional reset requirements this configuration completes within 1 second after the de assertion of fundamental reset The BIOS preconfigures the NT function BARSETUP registers the...

Page 729: ...to exchange messages and coordinate the programming of the NTB windows used for communication NTB windows for communication between the transparent switch s manager and any of the peer processors are...

Page 730: ...list is an immediate data transfer descriptor see section Immediate Data Transfer Descriptor on page 15 13 The immediate data transfer descriptor is configured such that The address in the descriptor...

Page 731: ...serial EEPROM configures the switch s automatic failover mechanism as follows Partition 0 is enabled to respond to failover capability 0 The FCAPSEL field in the SWPART0CTL register is set to 0x0 The...

Page 732: ...amming GPIOAFSEL and GPIOFUNC registers appropriately Refer to Chapter 13 General Purpose I O for details At this point the failover mechanism is armed A failover is triggered when the platform assert...

Page 733: ...lover configuration where the switch is configured with two switch parti tions each connected to a root complex and some endpoints The partitions are inter connected via an NTB which is used by the ro...

Page 734: ...SFMODE 0x5 i e primary and secondary failover mode is set to unattached port Ports 4 and 6 are configured to respond to primary and secondary failover events by programming fields in the SWPORT4FCTL a...

Page 735: ...ating mode is changed to unattached mode In addition ports 12 and 16 are reset and migrated to partition 0 Failover capability 1 is associated with partition 1 When a failover is triggered port 0 is r...

Page 736: ...rupt the root checks the source of this interrupt by inspecting the PCI to PCI bridge Interrupt Status P2PINTSTS Switch Event status SESTS and Switch Event Link Up Status SELINKUPSTS registers In this...

Page 737: ...the other root At this point the system has returned to its initial configuration If a new failover occurs the process is repeated To finalize the example after the reconfiguration initiated by RC1 R...

Page 738: ...n in port 8 in switch 2 switch receives the MSI and translates it across the NTB As a result the TLP is emitted by the NT function in port 0 of the 2 switch i e towards root complex 2 RC2 RC2 receives...

Page 739: ...te requests across port 8 s link to the NT function in port 8 of switch 1 The configuration write requests target the GASAADDR and GASADATA registers in this NT function i e function 0 such that RC2 h...

Page 740: ...ress specification are met RC2 proceeds to enumerate the downstream ports in switch 1 These ports are now part of the PCI Express hierarchy associated with RC2 To monitor the status of the link betwee...

Page 741: ...that the base address of the emitted NT multicast TLP be 0x00A0_0000 RC1 programs NT multicast egress processing in port 4 as follows NTMCOVR0C PART 0x1 i e NT multicast overlay register set 0 is asso...

Page 742: ...memory associated with RC1 RC2 and RC3 To do this RC0 sets up the DMA descriptors in its memory The data transfer descriptors are programmed such that the source address points to the location in RC0...

Page 743: ...IDT Usage Models PES32NT24xG2 User Manual 26 33 January 30 2013 Notes...

Page 744: ...IDT Usage Models PES32NT24xG2 User Manual 26 34 January 30 2013 Notes...

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