IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 629 / 744

IDT DMA Function Registers
PES32NT24xG2 User Manual 23 - 41 January 30, 2013
Notes
DMACEEM - DMA Correctable Error Emulation (0x40C)
31 ADVISORYNF RW 0x0
SWSticky
Advisory Non-Fatal Error Trigger.
If this bit is set together with another error bit in this register
for which an advisory non-fatal error is possible (refer to the
PCI Express Base Specification), an advisory non-fatal
error is logged an reported in the PCI-to-PCI bridge func-
tion’s AER capability structure, provided the error severity
for the selected uncorrectable error is configured such that
the error will be of type non-fatal.
If this bit is set together with another error bit in this register
for which an advisory non-fatal error is not possible, the
operation is undefined.
If this bit is set together with another error bit in this register
for which an advisory non-fatal error is possible, but the
severity of the selected uncorrectable error is fatal, then this
bit is ignored and the selected error is logged and reported
as a fatal error.
Bit
Field
Field
Name
Type Default
Value
Description
0 RCVERR RW 0x0
SWSticky
Receiver Error Trigger.
Writing a one to this bit causes the corresponding error bit
to get set in the PCI-to-PCI Bridge function’s AERCES reg-
ister. This bit always returns 0x0 when read.
5:1 Reserved RO 0x0 Reserved field.
6 BADTLP RW 0x0
SWSticky
Bad TLP Trigger.
Writing a one to this bit causes the corresponding error bit
to get set in the PCI-to-PCI Bridge function’s AERCES reg-
ister. This bit always returns 0x0 when read.
7 BADDLLP RW 0x0
SWSticky
Bad DLLP Trigger.
Writing a one to this bit causes the corresponding error bit
to get set in the PCI-to-PCI Bridge function’s AERCES reg-
ister. This bit always returns 0x0 when read.
8 RPLYROVR RW 0x0
SWSticky
Replay Number Rollover Trigger.
Writing a one to this bit causes the corresponding error bit
to get set in the PCI-to-PCI Bridge function’s AERCES reg-
ister. This bit always returns 0x0 when read.
11:9 Reserved RO 0x0 Reserved field.
12 RPLYTO RW 0x0
SWSticky
Replay Timer Timeout Trigger.
Writing a one to this bit causes the corresponding error bit
to get set in the PCI-to-PCI Bridge function’s AERCES reg-
ister. This bit always returns 0x0 when read.
13 Reserved RO 0x0 Reserved field.
14 CIE RW 0x0
SWSticky
Correctable Internal Error Trigger.
Writing a one to this bit causes the corresponding error bit
to get set in the PCI-to-PCI Bridge function’s AERCES reg-
ister. This bit always returns 0x0 when read.
Bit
Field
Field
Name
Type Default
Value
Description