IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 98 / 744

IDT Switch Core
PES32NT24xG2 User Manual 4 - 20 January 30, 2013
Notes
Each port is capable of notifying the detection of an AER error to other ports. Each port has an internal
non-software visible register named Port AER Status (PAERSTS) which provides a gathering point for
combined AER correctable and uncorrectable errors of all functions (e.g., PCI-to-PCI bridge, NT, and DMA)
in the port.
– Bits in this internal register have a transient nature (i.e., they are set by hardware when the error
is detected, and cleared by hardware as the error condition passes). As a result, this register is
not visible by software.
– Each bit in the PAERSTS register corresponds to an AER error (e.g., Data Link Protocol error,
Surprise Down error, etc.)
– The Internal Error (IE) bit in the PAERSTS register of a port is set when the port logs an internal
error that occurred in the port itself (i.e., errors logged in the IERRORSTS0 register).
• Note that the IE bit in the PAERSTS register is not set when a port logs an internal error originally
detected by another port (i.e., errors logged in the IERRORSTS1 register). This prevents a feed-
back when two ports monitor each other’s AER errors.
– Other bits in the PAERSTS register are set when the corresponding AER error is detected in any
of the port functions (i.e., the error is logged in the AERUES or AERCES register of any of the port
functions).
• Note that depending on the port operating mode, some functions are not present in the port.
These functions do not have effect on the port’s PAERSTS register.
Associated with the PAERSTS register is the software-visible Port AER Mask (PAERMSK) register. The
PAERMSK register determines which bits in the PAERSTS register result in a notification being sent to
other ports. When any unmasked bit is set in the PAERSTS register of a port, the port notifies all other ports
of the occurrence of an AER error. As a result, the bit corresponding to the port that detected the error (i.e.,
PxAER) is set in the IERRORSTS1 register of all other ports in the switch.
A port that detects an AER error does not notify itself (i.e., the IERRORSTS1 register of a port is not
affected by the PAERSTS register associated with that same port).
Figure 4.8 shows a simplified schematic of the connection described above. As shown, the internal error
detection logic in a port (e.g., Port 1) is capable of noticing the detection of AER errors by any other port in
the switch (e.g., Port 0). That is, when Port 0 detects an AER error in any of its functions, and that error is
unmasked in the PAERMSK register in Port 0, the error is notified to Port 1. In Port 1, the P0AER bit is set
in the IERRORSTS1 register. Port 1 can be configured to report that error as an AER correctable or uncor-
rectable internal error (refer to section Internal Errors on page 4-16). AER software can then service Port 1
appropriately. Such software can use the status in Port 1’s IERRORSTS0/1 register to determine the exact
cause of the internal error. In this example, software can determine that Port 0 had an AER error by noticing
that Port 1’s P0AER bit is set in the IERRORSTS1 register. This information can then be used to manage
the switch appropriately (e.g., reconfigure partitions, etc.)