IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 94 / 744

IDT Switch Core
PES32NT24xG2 User Manual 4 - 16 January 30, 2013
Notes
Internal Errors
Internal errors are errors which are associated with a PCI Express interface, which occur within a
component, and which may not be attributable to a packet or event on the PCI Express interface itself or on
behalf of transactions initiated on PCI Express.
The PES32NT24xG2 classifies the following IDT proprietary switch errors as internal errors:
– Switch core time-outs
– Single and double bit internal memory ECC errors.
– End-to-end data path parity protection errors
In addition, the switch offers a mechanism by which AER errors detected on a port may be reported as
internal errors in other ports. This mechanism is described in section Reporting of Port AER Errors as
Internal Errors on page 4-19. Internal errors are reported by the port in which they are detected through
AER as outlined in the PCI Express Base Specification. The reporting of internal errors in AER may be
disabled by clearing the Internal Error Reporting Enable (IERROREN) bit in the port’s Internal Error
Reporting Control (IERRORCTL) register.
The setting of the IERROREN bit in the IERRORCTL register affects all functions present in the port
(e.g., PCI-to-PCI bridge, NT function, and DMA function). When internal error reporting is disabled, the
following AER fields become read-only in all functions of the port:
– Uncorrectable Internal Error Status (UIE) field in the AERUES register
– Uncorrectable Internal Error Mask (UIE) field in the AERUEM register
– Uncorrectable Internal Error Severity (UIE) field in the AERUESV register
– Correctable Internal Error Status (CIE) field in the AERCES register
– Correctable Internal Error Mask (CIE) field in the AERCEM register
– Header Log Overflow Mask (HLO) field in the AERCEM register
The switch does not support recording of headers for uncorrectable internal errors. When an uncorrect-
able internal error is reported by AER, a header of all ones is recorded. It is possible to control the reporting
of internal errors detected by a port on a per-function basis. Each port function contains an Internal Error
Mask register that allows selection of which internal errors are reported on the function’s AER Capability
Structure.
– In the PCI-to-PCI bridge function, the P2PIERRORMSK0/1 registers provide this control.
– In the NT function, the NTIERRORMSK0/1 registers provide this control.
– In the DMA function, the DMAIERRORMSK0/1 registers provide this control.
By default, the following internal errors are reported only by the DMA function’s AER Capability Struc-
ture.
– DMA IFB timeout (for posted, non-posted, and completion TLPs)
– DMA IFB single and double bit errors (for control and data memories)
– DMA EFB single and double bit errors (for control and data memories)
– DMA end-to-end data-path parity error
In addition, internal errors caused by the mechanism described in section Reporting of Port AER Errors
as Internal Errors on page 4-19 are only reported by the PCI-to-PCI bridge function. All other internal errors
are reported by the AER Capability Structure in all functions present in the port (e.g., PCI-to-PCI bridge, NT,
and DMA). The functions present in the port depend on the port’s operating mode. Refer to Chapter 5,
Switch Partition and Port Configuration.
Corresponding to each possible internal error source is a status bit in the Internal Error Reporting Status
(IERRORSTS0/1) registers. A bit is set in the status register when the corresponding internal error is
detected. The purpose of the IERRORSTS0/1 registers is to log the specific internal error(s) detected by the
port. Software that is aware of the IERRORSTS0/1 registers can use this information to gain further insight
regarding the internal error(s) detected by a port. Software that is not aware of the IERRORSTS0/1 regis-
ters can ignore this register.