IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 398 / 744

IDT PCI-to-PCI Bridge Registers
PES32NT24xG2 User Manual 20 - 14 January 30, 2013
Notes
PCIEDCAP - PCI Express Device Capabilities (0x044)
Bit
Field
Field
Name
Type Default
Value
Description
2:0 MPAYLOAD RWL HWINIT
(See
description)
MSWSticky
Maximum Payload Size Supported.
This field indicates the maximum payload size that the
device can support for TLPs.
The default value of this field is automatically set by the
hardware based on the port’s maximum link width as deter-
mined by the stack’s configuration. If a port has a maximum
link width of x1, the default value of this field is 0x3. Other-
wise, the default value of this field is 0x4.
0x0 - (s128) 128 bytes max payload size
0x1 - (s256) 256 bytes max payload size
0x2 - (s512) 512 bytes max payload size
0x3 - (s1024) 1024 bytes max payload size
0x4 - (s2048) 2048 bytes max payload size
0x5 - Not supported
0x6 - reserved (treated as 128 bytes)
0x7 - reserved (treated as 128 bytes)
4:3 PFS RO 0x0 Phantom Functions Supported.
This field indicates the support for unclaimed function num-
ber to extend the number of outstanding transactions
allowed by logically combining unclaimed function numbers
with the TLP’s tag identifier. The value is hardwired to 0x0
to indicate that no function number bits are used for phan-
tom functions.
5 ETAG RWL 0x1
SWSticky
Extended Tag Field Support.
This field indicates the maximum supported size of the Tag
field as a requester.
0x0 - 5-bit Tag field supported
0x1 - 8-bit Tag field supported
8:6 E0AL RO 0x0 Endpoint L0s Acceptable Latency.
This field indicates the acceptable total latency that an end-
point can withstand due to transition from the L0s state to
the L0 state.
The value is hardwired to 0x0 as this field is only applicable
to endpoint functions.
11:9 E1AL RO 0x0 Endpoint L1 Acceptable Latency.
This field indicates the acceptable total latency that an end-
point can withstand due to transition from the L1 state to the
L0 state.
The value is hardwired to 0x0 as this field is only applicable
to endpoint functions.
12 ABP RO 0x0 Attention Button Present.
In PCI Express Specification 1.0a, when set, this bit indi-
cates that an Attention Button is implemented on the card/
module.
The value of this field is undefined in the PCI Express Base
Specification Rev. 2.1.
13 AIP RO 0x0 Attention Indicator Present.
In PCI Express base 1.0a when set, this bit indicates that
an Attention Indicator is implemented on the card/module.
The value of this field is undefined in the PCI Express Base
Specification Rev. 2.1.