IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 67 / 744

IDT Reset and Initialization
PES32NT24xG2 User Manual 3 - 3 January 30, 2013
Notes
– When serial EEPROM initialization completes, the EEPROM Done (EEPROMDONE) bit in the
SMBUSSTS register is set and the switch’s ports start processing configuration requests normally,
unless the RSTHALT bit in the SWCTL register is set. If serial EEPROM initialization completes
with an error, the RSTHALT bit in the SWCTL register is set as described in section Initialization
from Serial EEPROM on page 12-3. In this case, the ports remain a quasi-reset state as described
in step 11.
11. If the RSTHALT bit in the SWCTL register is set (e.g., due to the assertion of the RSTHALT signal in
the sampled boot vector), all ports enter (or remain) in a quasi-reset state. Otherwise, this step is
not executed.
– All ports remain in quasi-reset state until the Reset Halt (RSTHALT) bit is cleared by software in
the SWCTL register. This provides a synchronization point for a device on the slave SMBus to
initialize the device. When device initialization is completed, the slave SMBus device clears the
RSTHALT bit allowing the device to begin normal operation.
12. The Register Unlock (REGUNLOCK) bit is cleared in the Switch Control (SWCTL) register.
13. Normal device operation begins.
The PCI Express Base Specification 2.1 indicates that a device must respond to configuration request
transactions within 100ms from the end of Conventional Reset (cold, warm, or hot). Additionally, the PCI
Express Base Specification indicates that a device must respond to configuration requests with a
successful completion within 1.0 second after Conventional Reset of a device. The reset sequence above
guarantees that the switch will be ready to respond successfully to configuration requests within the 1.0
second period as long as the serial EEPROM initialization process completes within 200 ms.
– Under normal circumstances, 200 ms is more than adequate to initialize registers in the device
with a master SMBus operating frequency of 400 KHz.
Serial EEPROM initialization may cause writes to register fields that initiate side effects such as link
retraining. These side effects are initiated at the point at which the write occurs. Therefore, serial EEPROM
initialization should be structured in a manner so as to ensure proper configuration prior to initiation of these
side effects.
The operation of a switch fundamental reset with serial EEPROM initialization is illustrated in Figure 3.1.
Figure 3.1 Switch Fundamental Reset with Serial EEPROM Initialization
GCLK*
Vdd
PERSTN
SerDes
Master SMBus
Slave SMBus
CDR Lock
Link Ready
Ready for Normal Operation
Ready
Serial EEPROM Initialization
1. Clock not shown to scale
~285
μ
s
Ports held in Quasi-Reset Mode
Link Training PLL Reset & Lock
> 100ns
Stable
Power
Stable
GCLK
~2
μ
s
< 100 ms
< 200 ms
Ports begin to process TLPs normally