IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 129 / 744

Notes
PES32NT24xG2 User Manual 7 - 1 January 30, 2013
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Chapter 7
Link Operation
Overview
Link operation in the PES32NT24xG2 switch adheres to the PCI Express Base Specification Revision
2.1, supporting speeds of 2.5 GT/s and 5.0 GT/s. This chapter does not describe the controls related to the
Serializer-Deserializer (SerDes) block associated with each port. Refer to Chapter 8, SerDes, for a detailed
description of this topic.
Each port’s link operates independently from any other port. This chapter describes link operation from
the perspective of each port.
The behavior of the port’s link varies depending on whether the port is an upstream or downstream port.
In the PES32NT24xG2, each port supports upstream and downstream link behavior. The behavior is deter-
mined dynamically by the port’s operating mode (e.g., upstream switch port, downstream switch port, etc).
Refer to Chapter 5, Switch Partition and Port Configuration, for further details on port operating modes.
Depending on the port operating mode, a port may be configured with a single function or multiple func-
tions (i.e., PCI-to-PCI bridge, NT, and DMA). Multi-function ports follow the rules for multi-function devices
outlined in the PCI Express Base Specification 2.1.
In this specification, the term full link retrain is defined as retraining a link by transitioning through the
PHY’s LTSSM
1
Detect state.
Port Merging
Ports in the PES32NT24xG2 may be merged to increase the port’s maximum link width. Refer to section
Stack Configuration on page 3-5 for a description of the possible port configurations. As described in this
section, the switch allows up to eight x1 ports to be merged into a single x8 port. The merging of ports is
controlled by the stack configuration registers, as described in section Stack Configuration on page 3-5.
When ports are merged, the corresponding serial link pins (i.e., PExRP[], PExRN[], PExTP[], and
PExTN[]) associated with each of the merged ports form the merged link. Specifically, the serial link pins
associated with the lowest-numbered merged port correspond to the lowest numbered lanes of the merged
port’s link. The serial link pins associated with the highest-numbered merged port correspond to the highest
numbered lanes of the merged port’s link.
Note: Pin [x] of a port refers to a lane. For port 0, PE00RN[0] refers to lane 0, PE00RN[1] refers to
lane 1, etc.
For example, port 8 is associated with the PE08RP[0] serial pin. Similarly, port 9 is associated with the
PE09RP[0] serial pin. When these ports are merged into a x2 port, port 9 is de-activated
2
and port 8 uses
the pin associated with port 9’s link (i.e., PE09RP[0] is associated with port 8, lane 1; PE08RP[0] remains
associated with port 8, lane 0). The same applies to the other pins associated with the serial link (i.e.,
PExRN[], PExTP[], and PExTN[]) signals. Also, the MAXLNKWDTH field in port 8’s PCIELCAP register is
automatically set by the hardware to 0x2 (i.e., maximum link width is x2).
Port Maximum Link Width
The Maximum Link Width (MAXLNKWDTH) field in a port’s PCI Express Link Capabilities (PCIELCAP)
register indicates the maximum link width of the port based on the stack configuration at the time. There-
fore, when a stack is configured such that ports are merged, the MAXLNKWDTH field is automatically set
by the hardware to correctly indicate a merged port’s maximum link width.
1.
The term ‘LTSSM’ refers to a port’s Link Training and Status State Machine in the Physical Layer.
2.
Refer to section Stack Configuration on page 3-5 for a formal definition of the behavior of a deactivated port.