IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 229 / 744

IDT SMBus Interfaces
PES32NT24xG2 User Manual 12 - 25 January 30, 2013
Notes
Table 12.19 indicates the sequence of data as it is presented on the slave SMBus following the byte
address of the Slave SMBus interface. Dword addresses and not byte addresses must be used to access
all visible software registers. ADDRL and ADDUL represent the lower 8-bit of the doubleword system
address and upper 6-bit doubleword system address, respectively. For example, use ADDRU = x00 and
ADDRL = 0x00 to access system address 0x00000 (port 0’s Vendor/Device ID register). Use ADDRU = x00
and ADDRL = 0x01 to access system address 0x00004 (port 0’s Command/Status register).
The format of the CMD field is shown in Figure 12.10 and described in Table 12.20.
Figure 12.10 CSR Register Read or Write CMD Field Format
6 DATALM Data Lower Middle. Bits [15:8] of data doubleword.
7 DATAUM Data Upper Middle. Bits [23:16] of data doubleword.
8 DATAUU Data Upper. Bits [31:24] of data doubleword.
1.
Refer to section Overview on page 12-1 for details on PES32NT24xG2’s system addresses and the Global Address
Space. The SMBus slave interface is capable of addressing only the first 256KB (i.e., 2
16
DWords) of the Global Address
Space.
Bit
Field
Name Type Description
0 BELL Read/Write Byte Enable Lower. When set, the byte enable for bits [7:0] of the
data word is enabled.
1 BELM Read/Write Byte Enable Lower Middle. When set, the byte enable for bits [15:8]
of the data word is enabled.
2 BEUM Read/Write Byte Enable Upper Middle. When set, the byte enable for bits
[23:16] of the data word is enabled.
3 BEUU Read/Write Byte Enable Upper. When set, the byte enable for bits [31:24] of the
data word is enabled.
4 OP Read/Write CSR Operation. This field encodes the CSR operation to be per-
formed.
0 - CSR write
1 - CSR read
5 0 0 Reserved. Must be zero
6 RERR
1
Read-Only
and Clear
Read Error. This bit is set if the last CSR read SMBus transaction
was not claimed by the device. Success indicates that the transaction
was claimed, not necessarily that the operation completed without
error.
7 WERR
1
Read-Only
and Clear
Write Error. This bit is set if the last CSR write SMBus transaction
was not claimed by the device. Success indicates that the transaction
was claimed, not necessarily that the operation completed without
error.
Table 12.20 CSR Register Read or Write CMD Field Description
Byte
Position
Field
Name
Description
Table 12.19 CSR Register Read or Write Operation Byte Sequence (Part 2 of 2)
Bit
6
Bit
7
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
BELL BELM WERR BEUM BEUU OP RERR 0