IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 158 / 744

IDT SerDes
PES32NT24xG2 User Manual 8 - 10 January 30, 2013
Notes
When the PHY operates in low-swing mode, de-emphasis is automatically turned off. Therefore, the fine
and coarse de-emphasis controls in the S[x]TXLCTL0 and S[x]TXLCTL1 registers have no effect. In this
mode, the TDVL_LSG1 and TDVL_LSG2 fields in the S[x]TXLCTL1 register control the transmitter voltage
swing for Gen 1 and Gen 2 modes respectively. Refer to section Low-Swing Transmitter Voltage Mode on
page 8-12 for further details.
In addition to the SerDes settings described above, the user may apply an amplitude boost to the drive
swing by setting the TX_AMPBOOST field in the S[x]TXLCTL0 register. Amplitude boost may be applied on
a per-lane basis. Amplitude boost may be applied to increase the drive swings above the values shown in
Tables 8.6, 8.7, and 8.8. Refer to the description of the TX_AMPBOOST field for further details.
Programmable De-emphasis Adjustment
The tables shown in the previous section list different settings to control the SerDes drive swing while
keeping the de-emphasis within the nominal range, depending on the PHY operating mode (e.g., Gen 1
data rate and -3.5 dB de-emphasis, Gen 2 data rate and -3.5 dB de-emphasis, or Gen 2 data rate with -6.0
dB de-emphasis).
It is possible to modify the de-emphasis in fine or coarse increments on a per-lane basis, using the
appropriate fields in the S[x]TXLCTL0 and S[x]TXLCTL1 registers. Table 8.5 shows the register fields that
control fine and coarse de-emphasis for each PHY operating mode.
Figure 8.1 shows the qualitative relationship between the coarse and fine de-emphasis controls and the
resulting de-emphasis.
Figure 8.1 Relationship Between Coarse and Fine De-emphasis Controls
When using the de-emphasis controls, it is important to understand that the actual de-emphasis applied
on the link is a function of the de-emphasis controls, the transmit drive swing controls, and the data rate of
the SerDes.
The coarse de-emphasis controls should generally be set as shown in Tables 8.6, 8.7, and 8.8. Note
that there is a coarse de-emphasis control per PHY operating mode.
– When the PHY operates in Gen 1 data rate with -3.5 dB de-emphasis, the coarse de-emphasis is
controlled by the CDC_FS3DBG1 field in the S[x]TXLCTL1 register.
– When the PHY operates in Gen 2 data rate with -3.5 dB de-emphasis, the coarse de-emphasis is
controlled by the CDC_FS3DBG2 field in the S[x]TXLCTL1 register.
– When the PHY operates in Gen 2 data rate with -6.0 dB de-emphasis, the coarse de-emphasis is
controlled by the CDC_FS6DBG2 field in the S[x]TXLCTL1 register.
The coarse de-emphasis settings shown in Tables 8.6, 8.7, and 8.8 ensure that the de-emphasis falls
within the nominal range mandated by the PCI Express Base Specification.
0x0
Coarse De-emphasis Control
0x7
D
e
-e
m
p
h
asi
s (d
B
)
Fine De-emphasis Control
0x0
0x1
0x2
0x3