IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 675 / 744

IDT Switch Configuration and Status Registers
PES32NT24xG2 User Manual 24 - 27 January 30, 2013
Notes
S[7:0]CTL- SerDes x Control
Bit
Field
Field
Name
Type Default
Value
Description
4:0 LANESEL RW 0x10
SWSticky
Lane Select.
This field selects the lane on which the SerDes lane control
registers (S[x]TXLCTL0, S[x]TXLCTL1, S[x]RXLCTL, and
S[x]RXEQLCTL) operate when written.
0x0 - Operate on lane 0 only
0x1 - Operate on lane 1 only
0x2 - Operate on lane 2 only
0x3 - Operate on lane 3 only
0x10 - Operate on all lanes simultaneously
Others - Reserved
For example, when LANESEL=0x0, configuration writes to
the above listed registers affect lane 0 of the SerDes only.
When LANESEL=0x10, the settings in the SerDes lane
control registers are applied to all lanes simultaneously.
Read operations are not affected by this field (i.e., reading
from a SerDes lane control register returns the last value
written to that register, regardless of the setting of this field).
Operating on a reserved lane results in undefined conse-
quences.
5 POWERDN RW 0x0
SWSticky
SerDes Power-Down.
When this bit is set, the SerDes is placed in a deep low-
power state (i.e., the SerDes lanes are placed in P2 and the
CMU is powered-down). In addition, the PHY LTSSM in the
corresponding port(s) is immediately transitioned to the
Detect state.
When this bit is cleared, the SerDes is powered-on, initial-
ized, and the PHY LTSSM initiates link training.
This bit has no effect when the SerDes is already powered-
down (e.g., the SerDes quad associated with a disabled
port).
When a SerDes is powered-down, the serial Tx/Rx pins and
reference resistor pins may be left unconnected.
Refer to section SerDes Power Management on page 8-14
for further details on SerDes power management.
31:6 Reserved RO 0x0 Reserved field.