IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 140 / 744

IDT Link Operation
PES32NT24xG2 User Manual 7 - 12 January 30, 2013
Notes
Downstream Switch Port
A Set_Slot_Power_Limit message is generated and transmitted by downstream switch ports when
either of the following events occur:
– A configuration write is performed to the corresponding PCIESCAP register when the link associ-
ated with the downstream switch port is up.
– A link associated with the downstream switch port transitions from a non-operational state to an
operational (i.e., DL_Down to DL_Up) state.
Link Active State Power Management (ASPM)
The operation of link Active State Power Management (ASPM) is orthogonal to device power manage-
ment. Once ASPM is enabled, ASPM link state transitions are initiated by hardware without software
involvement. For a port operating in a multi-function mode, each function of the port has independent ASPM
settings. The switch follows the rules governing ASPM policy in multi-function devices, described in Section
5.4.1 of the PCI Express Base Specification.
The switch’s ASPM supports the L0s (receiver and transmitter) and L1 states. ASPM is enabled via the
ASPM field in the function’s link control register (PCIELCTL). Enabled ASPM settings that are common for
all functions of the port are enabled for the port as a whole.
In general, ASPM entry and exit conditions are based upon the port’s desire to transmit TLPs on the link.
For a port in multi-function mode (e.g., upstream switch port with NT function, NT with DMA function, etc.),
TLP transfers among functions in the port do not affect the ASPM state of the port, since the TLP transfer is
not destined to the multi-function port’s link. The only exception to this case is TLPs emitted by the DMA
function that map into the partition’s multicast BAR aperture, as these TLPs are routed to the port func-
tion(s) that claim the TLP as well as the port’s link (see section DMA Multicast on page 15-23).
L0s ASPM
L0s entry/exit operates independently for each direction of the link. On the receive side, the
PES32NT24xG2 upstream and downstream switch ports always respond to L0s entry/exit requests from
the link partner. On the transmit side, the L0s entry conditions must be met for 7µ s before the hardware
transitions the transmit link to the L0s state.
L0s Entry Conditions
The transmit side L0s entry conditions depend on the port’s operational mode (see Chapter 5). A port
configured in upstream switch port mode initiates L0s entry when all of the conditions listed below are met:
– L0s ASPM is enabled via the port’s PCIELCTL register.
– The following conditions are met for the amount of time specified above:
• The receive lanes of all of the switch downstream switch ports in the partition which are not in a
low power state (i.e., D3) and whose link is not down are in the L0s state.
• The port has no TLPs to transmit on the link (i.e., the port’s EFB is empty) or there are no avail-
able flow control credits to transmit a TLP.
• The port has no DLLPs pending for transmission.
A port configured in downstream switch port mode initiates L0s entry when all of the conditions listed
below are met:
– L0s ASPM is enabled via the port’s PCIELCTL register.
– The following conditions are met for the amount of time specified above:
• The receive lanes of the switch partition’s upstream port are in the L0s state.
• The port has no TLPs to transmit on the link (i.e., the port’s EFB is empty) or there are no avail-
able flow control credits to transmit a TLP.
• The port has no DLLPs pending for transmission.