IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 4 / 744

IDT
PES32NT24xG2 User Manual 2 January 30, 2013
Notes
Chapter 15, “DMA Controller,” describes how the PES32NT24xG2 supports two direct memory
access controller (DMA) functions.
Chapter 16, “Switch Events,” describes mechanisms provided by the PES32NT24xG2 to facilitate
communication between roots associated with different partitions as well as for communication between
these roots and a management agent.
Chapter 17, “Multicast,” describes how the multicast capability enables a single TLP to be forwarded
to multiple destinations.
Chapter 18, “Temperature Sensor,” provides a description of the on-chip temperature sensor with
three programmable temperature thresholds and a temperature history capability.
Chapter 19, “Register Organization,” describes the organization of all the software visible registers in
the PES32NT24xG2 and provides the address space for those registers.
Chapter 20, “PCI to PCI Bridge and Proprietary Port Specific Registers,” lists the Type 1 configura-
tion header registers in the PES32NT24xG2 and provides a description of each bit in those registers.
Chapter 21, “Proprietary Registers,” lists the proprietary registers in the PES32NT24xG2 and
provides a description of each bit in those registers.
Chapter 22, “NT Endpoint Registers,” lists the NT Endpoint registers in the PES32NT24xG2 and
provides a description of each bit in those registers.
Chapter 23, “DMA Registers,” lists the DMA registers in the PES32NT24xG2 and provides a descrip-
tion of each bit in those registers.
Chapter 24, “Switch Control Registers,” lists the switch control and status registers in the
PES32NT24xG2 and provides a description of each bit in those registers.
Chapter 25, “JTAG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic
TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.
Chapter 26, “Usage Models,” describes possible configurations of the PES32NT24xG2 switch and
presents some important system usage models.
Signal Nomenclature
To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms
assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or
true, independent of whether that level is represented by a high or low voltage. The term negate or negation
is used to indicate that a signal is inactive or false.
To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter-
preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks,
buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.
To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on
the right. No leading zeros will be included.
Throughout this manual, when describing signal transitions, the following terminology is used. Rising
edge indicates a low-to-high (0 to 1) transition. Falling edge indicates a high-to-low (1 to 0) transition. These
terms are illustrated in Figure 1.