IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 149 / 744

Notes
PES32NT24xG2 User Manual 8 - 1 January 30, 2013
®
Chapter 8
SerDes
Overview
This chapter describes the controllability of the Serialiazer-Deserializer (SerDes) block associated with
each PES32NT24xG2 port. A SerDes block is composed of the serializing/deserializing logic for four PCI
Express lanes (i.e., a SerDes “quad”), plus a central unit that controls the quad as a whole. This central unit
is called CMU, and contains functionality such as a PLL to generate a high-speed clock used by each lane,
initialization of the quad, etc.
In order to improve signal integrity across the high-speed PCI Express links, the PES32NT24xG2 allows
per-lane programmability of several SerDes settings. These include the following.
– Transmitter drive level
– Transmitter de-emphasis level
– Receiver equalization
In addition, the PES32NT24xG2 supports the optional “low-swing mode” specified by the PCI Express
Base Specification 2.1. This mode is intended for power-sensitive applications. This chapter describes
these controls, their intended use, and the manner in which they are programmed. Before this is discussed,
the topic of SerDes numbering and port association is introduced. To modify the SerDes driver and receiver
settings for a port, the SerDes quad and specific lanes associated with the port must be identified as
described in section SerDes Numbering and Port Association on page 8-1.
SerDes Numbering and Port Association
The PES32NT24xG2 contains eight SerDes quads, numbered 0 to 7. Tables 8.1 through 8.4 list the
ports in the switch and the SerDes quads with which they are associated. The SerDes/port association
depends on the configuration of the corresponding stack
1
, as shown in the tables.
– SerDes / Port association for stack configurations not shown in the tables can be easily derived
from the basic configurations shown in the table.
Note that in some stack configurations, several ports whose width is less than x4 share a SerDes quad
(i.e., a SerDes quad could be shared by four x1 ports or by two x2 ports). Still, the SerDes lanes associated
with different ports operate independently, such that the ports can operate at different data rates, power
states, drive and de-emphasis levels, etc.
– The exception to the above assertion is that all ports that share a SerDes quad must operate in
the same clocking mode. See section Port Clocking Modes on page 2-2 for further details on this.
To modify some of the SerDes driver and receiver settings (e.g., drive swing, receiver equalization) for a
port, the SerDes quad and specific lanes associated with the port must be identified via the tables shown
below.
– For example, as shown Table 8.1, lanes 3 and 2 of SerDes quad 1 are associated with port 3,
lanes 1 and 0 respectively. Therefore, to modify the SerDes driver and receiver settings of port 3,
the configuration registers associated with SerDes quad 1, lanes 3 and 2 should be modified. The
next sections describe the settings and corresponding configuration registers in detail.
1.
As mentioned in section Stack Configuration on page 3-5, the switch contains four stacks, two of which are
associated with 4 ports each and two of which are associated with 8 ports each. Refer to Stack Configuration for
further details.