
IDT Non-Transparent Switch Operation
PES32NT24xG2 User Manual
14 - 22
January 30, 2013
Notes
Maximum Payload Size
The PES32NT24xG2 requires that the Maximum Payload Size (MPS) field in the PCI Express Device
Control (PCIEDCTL) register be set identically in all functions (i.e., PCI-to-PCI bridge, NT, and DMA) of a
partition. In addition, when inter-partition transfers are possible between two or more partitions (i.e., across
the NT interconnect), all switch functions in these partitions must have the same MPS setting. Violating this
rule produces undefined results.
Note that a port with a maximum link width of x1 supports a Maximum Payload Size (MPS) of up to
1 KB. Ports with a maximum link width of x2, x4, or x8 support an MPS of up to 2 KB. The MPAY-
LOAD field in the PCI Express Device Capabilities (PCIEDCAP) register is automatically set by the
hardware based on the port’s maximum link width to reflect this.
Power Management
Refer to Chapter 9, Power Management.
Bus Locking
The NT function does not support bus locking. Memory read request-locked TLPs received by an NT
function are treated as unsupported requests and an unsupported request completion with no data (CplLk)
is returned. The operation of a switch partition is undefined when bus locking is performed in a partition that
contains an NT function in its upstream port.
ECRC Support
End-to-End CRC (ECRC) is supported for transactions that are forwarded through the NT interconnect.
Since the TLP contents (i.e., header) are modified for TLPs flowing between NT endpoints, a new ECRC
must be computed. When a TLP is forwarded on to the NT interconnect by an NT endpoint, the NT endpoint
computes the ECRC for the new translated TLP in parallel with checking the ECRC, if it exists, of the
received TLP. The existence of an ECRC in the received TLP is indicated by the TD bit in the TLP header.
The NT function only checks and logs ECRC errors when the ECRC Check Enable (ECRCCE) bit is set
in the function’s AER Control (AERCTL) register, and the TLP with ECRC is received from the upstream
port’s link.
–
ECRC error checking and logging is not performed by the NT function when it does not receive
the TLP from the link.
• In this case, the ECRC error checking and logging is done by the port that received the TLP from
the link (e.g., downstream port).
–
If the port is operating in a multi-function mode, then ECRC errors are only logged in functions in
which ECRC checking is enabled.
If ECRC checking applicable as described above and an ECRC error is detected, then an ECRC error is
reported by the NT endpoint that received the TLP. See section Error Detection and Handling by the NT
Function on page 14-25 for details.
–
If ECRC checking is enabled in an NT endpoint, then ECRC is checked in all TLPs received by
the NT endpoint that contain an ECRC. The reception of a TLP without ECRC is not considered
an error (i.e., the TLP is processed normally).
ECRC generation is enabled in the NT endpoint when the ECRC Generation Enable (ECRCGE) bit is
set in the function’s AER Control (AERCTL) register.
If ECRC generation is enabled in the NT endpoint associated with the destination partition of the trans-
lated TLP, then the translated TLP contains an ECRC and the TD bit in the translated TLP header is set.
–
If ECRC checking is not enabled in the NT endpoint that received the TLP, or if the received TLP
does not contain an ECRC, or if ECRC checking is enabled and the ECRC computed by the NT
endpoint is correct, then the ECRC associated with the translated TLP is that computed by the NT
endpoint associated with the destination partition.
Summary of Contents for PCI Express 89HPES32NT24xG2
Page 20: ...IDT Table of Contents PES32NT24xG2 User Manual x January 30 2013 Notes...
Page 24: ...IDT List of Tables PES32NT24xG2 User Manual xiv January 30 2013 Notes...
Page 28: ...IDT List of Figures PES32NT24xG2 User Manual xviii January 30 2013 Notes...
Page 56: ...IDT PES32NT24xG2 Device Overview PES32NT24xG2 User Manual 1 20 January 30 2013 Notes...
Page 100: ...IDT Switch Core PES32NT24xG2 User Manual 4 22 January 30 2013 Notes...
Page 128: ...IDT Failover PES32NT24xG2 User Manual 6 4 January 30 2013 Notes...
Page 148: ...IDT Link Operation PES32NT24xG2 User Manual 7 20 January 30 2013 Notes...
Page 164: ...IDT SerDes PES32NT24xG2 User Manual 8 16 January 30 2013 Notes...
Page 170: ...IDT Power Management PES32NT24xG2 User Manual 9 6 January 30 2013 Notes...
Page 196: ...IDT Transparent Switch Operation PES32NT24xG2 User Manual 10 26 January 30 2013 Notes...
Page 244: ...IDT SMBus Interfaces PES32NT24xG2 User Manual 12 40 January 30 2013 Notes...
Page 247: ...IDT General Purpose I O PES32NT24xG2 User Manual 13 3 January 30 2013 Notes...
Page 248: ...IDT General Purpose I O PES32NT24xG2 User Manual 13 4 January 30 2013 Notes...
Page 330: ...IDT Switch Events PES32NT24xG2 User Manual 16 6 January 30 2013 Notes...
Page 342: ...IDT Multicast PES32NT24xG2 User Manual 17 12 January 30 2013 Notes...
Page 344: ...IDT Temperature Sensor PES32NT24xG2 User Manual 18 2 January 30 2013 Notes...
Page 384: ...IDT Register Organization PES32NT24xG2 User Manual 19 40 January 30 2013...
Page 492: ...IDT Proprietary Port Specific Registers PES32NT24xG2 User Manual 21 44 January 30 2013 Notes...
Page 588: ...IDT NT Endpoint Registers PES32NT24xG2 User Manual 22 96 January 30 2013 Notes...
Page 710: ...IDT JTAG Boundary Scan PES32NT24xG2 User Manual 25 12 January 30 2013 Notes...
Page 743: ...IDT Usage Models PES32NT24xG2 User Manual 26 33 January 30 2013 Notes...
Page 744: ...IDT Usage Models PES32NT24xG2 User Manual 26 34 January 30 2013 Notes...