IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 387 / 744

IDT PCI-to-PCI Bridge Registers
PES32NT24xG2 User Manual 20 - 3 January 30, 2013
Notes
PCISTS - PCI Status Register (0x006)
9 FB2B RO 0x0 Fast Back-to-Back Enable.
Not applicable.
10 INTXD RW 0x0 INTx Disable.
Controls the ability of the PCI-to-PCI bridge to generate an
INTx interrupt message.
When this bit is set, any interrupts generated by this bridge
are negated. This may result in a change in the resolved
interrupt state of the bridge.
This bit has no effect on interrupts forwarded from the sec-
ondary to the primary interface.
15:11 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
2:0 Reserved RO 0x0 Reserved field.
3 INTS RO 0x0 INTx Status.
This bit is set when an INTx interrupt is pending from the
function.
INTx emulation interrupts forwarded by switch ports from
devices downstream of the bridge are not reflected in this
bit.
For downstream switch ports, this bit is set if an interrupt
has been “asserted” by the corresponding port’s hot-plug
controller.
4 CAPL RO 0x1 Capabilities List.
This bit is hardwired to one to indicate that the bridge imple-
ments an extended capability list item.
5 C66MHZ RO 0x0 66 MHz Capable.
Not applicable.
6 Reserved RO 0x0 Reserved field.
7 FB2B RO 0x0 Fast Back-to-Back (FB2B).
Not applicable.
8 MDPED RW1C 0x0 Master Data Parity Error Detected.
This bit is set by the bridge function if the PERRE bit in the
PCI Command register (PCICMD) is set to 0x1 and either of
the following two conditions occurs:
1) The function receives a Poisoned Completion going
Downstream.
2) The function transmits a Poisoned Request Upstream.
10:9 DEVT RO 0x0 DEVSEL# TIming.
Not applicable.
11 STAS RW1C 0x0 Signaled Target Abort.
This bit is set when the bridge completes a posted or non-
posted request with a completer-abort error
1
. In the switch,
this bit is set when the bridge blocks a multicast TLP
received on its primary side.
Bit
Field
Field
Name
Type Default
Value
Description