IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 153 / 744

IDT SerDes
PES32NT24xG2 User Manual 8 - 5 January 30, 2013
Notes
Programmable Voltage Margining and De-Emphasis
The PES32NT24xG2 contains SerDes transmitter voltage controls, which operate on a per-port, per-
quad, or per-lane basis. There are two mechanisms to control the SerDes transmitter voltage level:
– Via the Transmit Margin (TM) field of the associated port’s Link Control 2 Register (PCIELCTL2).
– Via proprietary SerDes transmitter control registers
• These registers are associated with each SerDes quad. Each SerDes quad has independent
transmitter control registers. To modify the settings for the lanes of a port, the SerDes quad
associated with the port must first be determined. The association between SerDes quads and
ports is described in section SerDes Numbering and Port Association on page 8-1. As indicated
in that section, the SerDes lanes associated with each port depend on the configuration of the
stack associated with the port.
• The SerDes Lane Transmitter Control Registers (S[x]TXLCTL0 and S[x]TXLCTL1, where ‘x’
refers to the SerDes quad number) are the registers that control the transmit settings of the
corresponding SerDes quad. S[0]TXLCTL0 and S[0]TXLCTL1 are associated with SerDes quad
0, S[1]TXLCTL0 and S[1]TXLCTL1 are associated with SerDes quad 1, and so on.
• The S[x]TXLCTL0 and S[x]TXLCTL1 registers may be used to control transmit driver settings
per-lane.
1
The selection of which of the two mechanism controls the SerDes transmit voltage is based on the
setting of the TM field in the associated port’s PCIELCTL2 register.
When the Transmit Margin (TM) field in the port’s PCIELCTL2 register is set to ‘Normal Operating
Range’, the transmitter voltage level for each SerDes lane of the port is controlled via the corresponding
S[x]TXLCTL0 and S[x]TXLCTL1 registers. Otherwise, the TM field controls the SerDes voltage directly for
all SerDes lanes associated with the port.
– For instance, when port 0 is configured as a x4 port, it is associated with SerDes quad 0, lanes 3
to 0 (see Table 8.1). If the TM field in the port’s PCIELCTL2 register is set to ‘Normal Operating
Range’, then the S[0]TXLCTL0 and S[0]TXLCTL1 registers control the operating voltage of the
port’s SerDes lanes. If the TM field is set to another value, the voltage on the SerDes lanes asso-
ciated with port 0 is set to the value in the port’s PCIELCTL2.TM field.
– As another example, when port 4 is configured as a x2 port, it is associated with SerDes quad 2,
lanes 0 and 1 (see Table 8.2). If the TM field in the port’s PCIELCTL2 register is set to ‘Normal
Operating Range’, then the S[2]TXLCTL0 and S[2]TXLCTL1 registers control the operating
voltage of the port’s SerDes lanes. These registers must be configured to operate on lanes 0 and
1 in order to affect the lanes associated with port 4. If the TM field is set to another value, the
voltage on the SerDes lanes associated with port 4 is set to the value in the port’s PCIELCTL2.TM
field.
– As a final example, when port 16 is configured as a x8 port, it is associated with SerDes quads 6
and 7 (see Table 8.4). If the TM field in the port’s PCIELCTL2 register is set to ‘Normal Operating
Range’, then the S[6]TXLCTL0, S[6]TXLCTL1, S[7]TXLCTL0, and S[7]TXLCTL1 registers control
the operating voltage of the port’s SerDes lanes. If the TM field is set to another value, the voltage
on the SerDes lanes associated with port 16 is set to the value in the port’s PCIELCTL2.TM field.
De-emphasis levels may also be adjusted on a per-lane basis, using the above mentioned transmitter
control registers. Nominally, de-emphasis levels are set to -3.5 dB, -6.0 dB, or 0 dB (in low-swing mode).
The S[x]TXLCTL0 and S[x]TXLCTL1 registers can be used to modify the nominal values by coarse or fine
steps.
1.
The S[x]TXLCTL0 and S[x]TXLCTL1 registers are used in conjunction with the SerDes Control (S[x]CTL)
register in order to apply the settings to a particular lane or all lanes of the SerDes. Please refer to the description
of the S[x]CTL register for further details.