IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 348 / 744

IDT Register Organization
PES32NT24xG2 User Manual 19 - 4 January 30, 2013
Notes
Address Maps
This section describes the address maps for regions of the global address space outlined in Table 19.1.
Reserved address ranges are outlined in Table 19.1. Reading from a reserved address range returns and
undefined value. Writes to a reserved address range complete successfully and have an undefined
behavior.
PCI-to-PCI Bridge Function Registers
This section outlines the configuration space associated with a PCI-to-PCI bridge function. These regis-
ters are accessible via PCI Express configuration requests to function 0 when the port is configured in the
following modes.
– Upstream switch port
– Upstream switch port with DMA function
– Upstream switch port with NT function
– Upstream switch port with NT and DMA functions
– Downstream switch port
These registers are not directly accessible by PCI Express configuration request when a port is config-
ured to operate in the following modes.
– Disabled
– Unattached
– NT function
– NT with DMA function
These registers are always accessible, regardless of the port mode, using global address space access
registers (i.e., GASAADDR and GASADATA located in each switch function), via the SMBus slave inter-
face, or via serial EEPROM.
– Access to the Extended Configuration Space Address indirection registers (i.e., ECFGADDR and
ECFGDATA) located in the PCI-to-PCI Bridge function is not allowed via the GASAADDR and
GASADATA registers.
The PCI-to-PCI bridge function configuration space contains standard
1
registers and capabilities
defined for PCI Express, as well as proprietary registers associated with proprietary port-specific features.
– section PCI-to-PCI Bridge Registers on page 19-5 lists the configuration registers defined by PCI
Express.
– section Proprietary Port-Specific Registers in the PCI-to-PCI Bridge Function on page 19-11 lists
the proprietary port-specific registers.
Figure 20.1 shows the organization of the configuration space for the PCI-to-PCI bridge function.
– Registers with offsets between 0x000 and 0x0FF are associated with PCI Express configuration
space.
– Registers with offsets between 0x100 and 0x3FF are associated with PCI Express extended
configuration space.
Registers with offsets between 0x400 and 0xFFF are associated with PCI Express extended configura-
tion space but are used for IDT proprietary port-specific registers
• IDT proprietary port-specific registers are described in section Proprietary Port-Specific Regis-
ters in the PCI-to-PCI Bridge Function on page 19-11.
– In order to facilitate access to the PCI Express extended configuration space by legacy PCI soft-
ware, the PCI-to-PCI bridge configuration space contains the Extended Configuration Space
Access Address and Data indirection registers (ECFGADDR and ECFGDATA). Refer to the defi-
nition of these registers for further details.
• The ECFGADDR and ECFGDATA registers can’t be used to access the global address space
access registers (i.e., GASAADDR and GASADATA).
1.
I.e., Registers defined by PCI Express Base Specification 2.1, PCI Local Bus Specification Revision 3.0, and
PCI-to-PCI Bridge Architecture Specification Revision 1.2.