IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 146 / 744

IDT Link Operation
PES32NT24xG2 User Manual 7 - 18 January 30, 2013
Notes
Link Disable Operation on a Crosslink
When a port is crosslinked, link disable operates as follows.
– For a port operating in downstream switch port mode:
• Regardless of the port’s physical layer mode of operation (i.e., downstream lanes or upstream
lanes):
If a higher layer directs the port to disable the link (i.e., the Link Disable (LDIS) bit is set in
the port’s PCIELCTL register), the physical layer enters the recovery state and proceeds
to the disabled state, as specified in the PCI Express Base Specification.
The physical layer responds to the reception of training sets with the disabled bit set by
transitioning to the disabled state as specified in the PCI Express Base Specification.
– For a port operating in upstream switch port mode:
• There is no higher layer mechanism to place the port’s link in the disabled state.
1
• Regardless of the port’s physical layer mode of operation (i.e., downstream lanes or upstream
lanes), the physical layer responds to the reception of training sets with the disabled bit set by
transitioning to the disabled state as specified in the PCI Express Base Specification.
Gen 1 Compatibility Mode
PES32NT24xG2 ports may be configured to operate in ‘Gen 1 Compatibility Mode’. The intent of this
mode is to overcome interoperability problems that arise when PCI Express Base 2.1 devices link train with
devices that conform to the PCI Express Base 1.1 or earlier specifications (i.e., Gen 1 devices). Specifically,
this mode overcomes the problem in which Gen 1 devices react incorrectly to newly defined bits in the PCI
Express Base Specification 2.1 for the PHY training sets. Such bits include bits 2, 6, and 7 in symbol four of
the TS1 and TS2 training sets.
A switch port is placed in Gen 1 Compatibility Mode by setting the Gen 1 Compatibility Mode Enable
(G1CME) bit in the PHYLCFG0 register and fully retraining the link (i.e., via the FLRET bit the
PHYLSTATE0 register). These registers are located in the proprietary port-specific registers located in the
PCI-to-PCI bridge function’s configuration space (see section Proprietary Port-Specific Registers in the
PCI-to-PCI Bridge Function on page 19-11).
When a switch port operates in Gen 1 Compatibility Mode, the PHY does not set the bits listed in Table
7.2 in the training sets that it transmits.
1.
Note that a port that is placed in the disabled operating mode (see section Switch Ports on page 5-5) does not
place its physical layer in the disabled state, but rather transitions the physical layer directly to the detect state.
Training
Set
Symbol Bit
PCI Express
Base 1.1 and
earlier
Definition
PCI Express Base 2.1
Definition
TS1 4 2 Reserved 5.0 GT/s Data Rate Support
6 Multiple meanings (refer to PCI Express
Base 2.1 Specification)
7 Speed Change
TS2 4 2 Reserved 5.0 GT/s Data Rate Support
6 Multiple meanings (refer to PCI Express
Base 2.1 Specification)
7 Speed Change
Table 7.2 Gen 1 Compatibility Mode: bits cleared in training sets