IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 669 / 744

IDT Switch Configuration and Status Registers
PES32NT24xG2 User Manual 24 - 21 January 30, 2013
Notes
SEPMSK - Switch Event Partition Mask (0x0C08)
24 P16AER RW 0x1
SWSticky
Port 16 AER Error.
When this bit is set, the corresponding bit in the SESTS
register is masked from generating a switch event.
25 P17AER RW 0x1
SWSticky
Port 17 AER Error
When this bit is set, the corresponding bit in the SESTS
register is masked from generating a switch event.
26 P18AER RW 0x1
SWSticky
Port 18 AER Error.
When this bit is set, the corresponding bit in the SESTS
register is masked from generating a switch event.
27 P19AER RW 0x1
SWSticky
Port 19 AER Error.
When this bit is set, the corresponding bit in the SESTS
register is masked from generating a switch event.
28 P20AER RW 0x1
SWSticky
Port 20 AER Error.
When this bit is set, the corresponding bit in the SESTS
register is masked from generating a switch event.
29 P21AER RW 0x1
SWSticky
Port 21 AER Error.
When this bit is set, the corresponding bit in the SESTS
register is masked from generating a switch event.
30 P22AER RW 0x1
SWSticky
Port 22 AER Error.
When this bit is set, the corresponding bit in the SESTS
register is masked from generating a switch event.
31 P23AER RW 0x1
SWSticky
Port 23 AER Error.
When this bit is set, the corresponding bit in the SESTS
register is masked from generating a switch event.
Bit
Field
Field
Name
Type Default
Value
Description
7:0 PMSK RW 0xFF
SWSticky
Partition Mask.
Each bit in this field corresponds to a switch partition.
When a bit in this field is set, switch events are masked to
the corresponding partition.
Bits associated with a partition not present in a product
option have no effect on the operation of the device (i.e.,
they are a don’t care).
31:8 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description