IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 239 / 744

IDT SMBus Interfaces
PES32NT24xG2 User Manual 12 - 35 January 30, 2013
Notes
Step 2. Prepare the I2C byte array
Table 12.29 shows the block byte array assignments (in increasing index order starting from index 0).
Address offset 0 is used in the examples.
Index 0 - Initialize the command code byte
CCode_i |= CCode_Block
CCode = 0x03 | 0x40 = 0x43
0x43 = (start bit= 1, end bit= 1, function_bits= CSR, size_bits= BLOCK)
Index 1 - Set the byte count
BKCnt_i = TranSize_BkWtHeader
BKCnt = 3
Index 2 - Set the dword option (BELL, BELM, BEUM, BEUU), and CSR READ operation
(OPRD)
BKCmd_i = CMD_Init | CMD_DWORD | CMD_OPRD
BKCmd = 0x00 | 0x0F | 0x10 = 0x1F
Index 3 - Set the lower CSR register offset
BKOfL_i = CSR_Offset & 0xFF
BKOfL = 0x00 & 0xFF = 0
Index 4 - Set the upper CSR register offset
BKOfU_i = (CSR_Offset & 0xFF00) >> 8
BKOfU = (0x00 & 0xFF00) >> 8 = 0
Step 3. Calculate the transaction size and read length
TranSize = TranSize_ 1
ReadLength = TranSize_BkRdHeader
Examples of Setting Up the I2C CSR Byte Sequence for a CSR Register
Write
The following examples are for the CSR byte sequence array write operations. There are three exam-
ples: BYTE write, WORD write, and DWORD write. Refer to Table 12.26 for the constant variables used in
the examples. In the CSR write operation, the data bytes in the CSR byte sequence are used. Please refer
to Table 12.23 for more information about the byte index locations.
In the following examples, "data" is a variable that is arbitrarily set to 0xBBAA2211.
Step 1. Initialize a CSR register offset variable and a command code init variable
CSR_Offset = address shifted by 2 bits to the right
CCode_i = CCode_Init
Index # Assignment Description
0 CCode_i |= CCode_Block
1 BKCnt_i = TranSize_BkWtHeader
2 BKCmd_i = CMD_Init | CMD_DWORD | CMD_OPRD
3 BKOfL_i = CSR_Offset & 0xFF
4 BKOfU_i = (CSR_Offset & 0xFF00) >> 8
Table 12.29 I2C Command Byte Array Indices