IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 290 / 744

IDT DMA Controller
PES32NT24xG2 User Manual 15 - 2 January 30, 2013
Notes
DMA descriptors, DMA source addresses from where data is read, and DMA destination addresses to
where data is written may be located anywhere in the PCI Express memory address space.
– Memory holding DMA descriptors may be located above the upstream port, below a downstream
switch port, or in another partition and accessed through an NT endpoint.
• A DMA descriptor must not be placed at memory address 0x0, as this address is used to indicate
the end of a descriptor list (see section DMA Descriptors on page 15-6).
– DMA memory-to-memory transfers may be performed without limitations between any two
memory regions accessible from the PCI Express hierarchy associated with which the DMA
channel is associated.
• between memory associated with an upstream port and a downstream switch port
• between memory associated with two downstream switch ports
• between two memory regions associated with a single upstream port or single downstream
switch port
• between memory associated with any port and memory in another partition via an NT endpoint
• between two memory regions associated with another partition via an NT endpoint
• from any memory region to multiple memory regions, as described above, utilizing multicast
– If the DMA BAR is enabled (section Base Address Registers on page 15-1), the memory regions
used for DMA transfers must not overlap with the DMA BAR aperture in memory space. When this
occurs, the operation of the DMA is undefined.
Data Transfer and Addressing
Figure 15.1 conceptually illustrates a data transfer operation performed by a DMA channel.
– The DMA channel issues memory read requests TLPs (i.e., MRd) to read data from source
memory.
– The source memory responds to a memory read request with one or more completion (Cpl) TLPs
that contain the requested data. These completions target the DMA channel.
– When a DMA channel receives a completion, it transforms the completion into a memory write
request TLP (i.e., MWr) to destination memory.
Figure 15.1 DMA Data Transfer
The determination of what data to read from source memory and where to write this data to destination
memory is referred to as the DMA addressing.
DMA Channel
Source Memory
MRd
Cpl
Data
Destination Memory
MWr
Data