IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 145 / 744

IDT Link Operation
PES32NT24xG2 User Manual 7 - 17 January 30, 2013
Notes
Crosslink
PES32NT24xG2 ports support the optional crosslink capability specified in the PCI Express Base Spec-
ification. Per this specification, a crosslink is established between two downstream switch ports or two
upstream ports. The device’s ports are capable of establishing crosslink with any link partner, including
another switch port.
When two PES32NT24xG2 switches are crosslinked to each other, it is recommended that the crosslink
connection be done among ports in different port groups, as shown in Table 7.1. In order for ports in the
same port group (e.g., port 0 and port 4, port 3 and port 7, etc.) to form a crosslink, software must set the
SEED field in the crosslinked port’s Phy PRBS Seed (PHYPRBS) register to different values.
Note that when an upstream port is crosslinked to another upstream port, neither port may automatically
initiate a link speed change to Gen 2, thereby resulting in a Gen 1 link. It is possible to overcome this by
clearing the ILSCC bit in the upstream port’s PHYLCFG0 register. By clearing this bit, the upstream port will
initiate the link transition to Gen 2 speed.
Crosslink is enabled by default. Crosslink may be disabled by setting the Crosslink Disable (CLINKDIS)
bit in the port’s Phy Link Configuration 0 (PHYLCFG0) register.
Hot Reset Operation on a Crosslink
When a PES32NT24xG2 port forms a crosslink, hot reset operates as follows.
– For a port operating in downstream switch port mode:
• Regardless of the port’s physical layer mode of operation (i.e., downstream lanes or upstream
lanes):
If a higher layer directs the port to hot reset (e.g., partition hot reset, upstream secondary
hot reset, downstream secondary hot reset), the physical layer enters the recovery state
and proceeds to the hot reset state, as specified in the PCI Express Base Specification.
The physical layer responds to the reception of training sets with the hot reset bit set by
transitioning to the hot reset state as specified in the PCI Express Base Specification. The
hot reset does not reset the configuration registers of the port and does not affect other
ports in the partition.
– For a port operating in upstream switch port mode:
• There is no higher layer mechanism to place the port in hot reset state.
• Regardless of the port’s physical layer mode of operation (i.e., downstream lanes or upstream
lanes), the physical layer responds to the reception of training sets with the hot reset bit set by
transitioning to the hot reset state. The hot reset has the effect described in section Partition Hot
Reset on page 3-12.
Port Groups
Group 0 Group 1 Group 2 Group 3
0 1 2 3
4 5 6 7
8 9 10 11
12 13 14 15
16 17 18 19
20 21 22 23
Table 7.1 Crosslink Port Groups