IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 63 / 744

IDT Clocking
PES32NT24xG2 User Manual 2 - 7 January 30, 2013
Notes
The port clocking mode associated with a port may be modified at any time, with the only requirement
being that the reference clock that will be used by the port after the port’s clocking mode is modified must
be stable prior to the modification. Modifying a port’s clocking mode causes the port’s PHY to transition to
the Detect state.
– This is not considered a surprise link down event.
If the clock mode change requires a modification of the reference clock associated with the port’s
SerDes, the SerDes is re-initialized. If the port is not in disabled mode, the PHY retrains the link.
Modifying a port’s clock mode is subject to the following restrictions outlined in Table 2.6 regarding the
clock frequencies.
CLKMODE[1:0]
Value in Boot
Configuration
Vector
Port 0
Clocking Mode
Port 0
SCLK
Port [23:1]
Clocking Mode
Port [23:1]
SCLK
0 Global Clocked 0
(non-common
clocked)
Global Clocked 0
(non-common
clocked)
1 Global Clocked 1
(common
clocked)
Global Clocked 0
(non-common
clocked)
2 Global Clocked 0
(non-common
clocked)
Global Clocked 1
(common
clocked)
3 Global Clocked 1
(common
clocked)
Global Clocked 1
(common
clocked)
Table 2.5 Initial Port Clocking Mode and Slot Clock Configuration State
Initial Port
Clock Mode
Subsequent Port
Clock Mode
Change by
Programming
the PCLKMODE
Register
Limitations / Caveats
Global Clocked Mode Local Port Clocked Mode If the GCLK operates at a nominal frequency of
100 Mhz, the port’s PxCLK must also operate at
a nominal frequency of 100 Mhz.
If the GCLK operates at a nominal frequency of
125 Mhz, the port’s PxCLK must also operate at
a nominal frequency of 125 Mhz.
Per the rules outlined in section Support for
Spread Spectrum Clocking (SSC) on page 2-5,
this port mode change is only allowed when the
GCLK does not have SSC. Still, the PxCLK is
allowed to have an SSC component on top of
the frequencies described above.
Local Port Clocked Mode Global Clocked Mode This port clock mode change is only allowed if
the global clock (GCLK) frequency is 100 Mhz
(as indicated by the GCLKFSEL pin).
Table 2.6 Clock Frequency Limitations when Modifying a Port’s Clock Mode