IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 458 / 744

IDT Proprietary Port Specific Registers
PES32NT24xG2 User Manual 21 - 10 January 30, 2013
Notes
IERRORSTS1 - Internal Error Reporting Status 1 (0x488)
30:29 Reserved RO 0x0 Reserved field.
31 DE2EPE RW1C 0x0
SWSticky
DMA End-to-End Data Path Parity Error.
This bit is set when an end-to-end data path parity error is
detected by the DMA.
This bit is only applicable for ports that contain a DMA func-
tion. When not applicable, this bit is hardwired to 0x0.
Bit
Field
Field
Name
Type Default
Value
Description
0 P0AER RW1C 0x0
SWSticky
Port 0 AER Error.
This bit is at the time that port 0 detects an AER error in one
of its functions and the error is not masked by the corre-
sponding Port AER Mask (PAERMSK) register.
1 P1AER RW1C 0x0
SWSticky
Port 1 AER Error.
This bit is at the time that port 1 detects an AER error in one
of its functions and the error is not masked by the corre-
sponding Port AER Mask (PAERMSK) register.
2 P2AER RW1C 0x0
SWSticky
Port 2 AER Error.
This bit is at the time that port 2 detects an AER error in one
of its functions and the error is not masked by the corre-
sponding Port AER Mask (PAERMSK) register.
3 P3AER RW1C 0x0
SWSticky
Port 3 AER Error.
This bit is at the time that port 3 detects an AER error in one
of its functions and the error is not masked by the corre-
sponding Port AER Mask (PAERMSK) register.
4 P4AER RW1C 0x0
SWSticky
Port 4 AER Error.
This bit is at the time that port 4 detects an AER error in one
of its functions and the error is not masked by the corre-
sponding Port AER Mask (PAERMSK) register.
5 P5AER RW1C 0x0
SWSticky
Port 5 AER Error.
This bit is at the time that port 5 detects an AER error in one
of its functions and the error is not masked by the corre-
sponding Port AER Mask (PAERMSK) register.
6 P6AER RW1C 0x0
SWSticky
Port 6 AER Error.
This bit is at the time that port 6 detects an AER error in one
of its functions and the error is not masked by the corre-
sponding Port AER Mask (PAERMSK) register.
7 P7AER RW1C 0x0
SWSticky
Port 7 AER Error.
This bit is at the time that port 7 detects an AER error in one
of its functions and the error is not masked by the corre-
sponding Port AER Mask (PAERMSK) register.
8 P8AER RW1C 0x0
SWSticky
Port 8 AER Error.
This bit is at the time that port 8 detects an AER error in one
of its functions and the error is not masked by the corre-
sponding Port AER Mask (PAERMSK) register.
Bit
Field
Field
Name
Type Default
Value
Description