IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 172 / 744

IDT Transparent Switch Operation
PES32NT24xG2 User Manual 10 - 2 January 30, 2013
Notes
Virtual Channel Support
In section Virtual Channel Support on page 4-5 there is a description of virtual channel support in the
PES32NT24xG2 ports. The PCI-to-PCI bridge function contains a VC Capability Structure that provides
architected port arbitration and TC/VC mapping for VC0. For port operating modes in which the PCI-to-PCI
bridge function is function 0 of the port, the VC Capability Structure in this function provides architected port
arbitration and TC/VC mapping for all functions of the port. For other port operating modes, the registers in
the PCI-to-PCI bridge function’s VC Capability Structure are ‘reserved’
1
and must not be programmed.
Maximum Payload Size
The PES32NT24xG2 requires that the Maximum Payload Size (MPS) field in the PCI Express Device
Control (PCIEDCTL) register be set identically in all functions (i.e., PCI-to-PCI bridge, NT, and DMA) of a
partition.
Note that a port with a maximum link width of x1 supports a Maximum Payload Size (MPS) of up to 1
KB. Ports with maximum link width of x2, x4, or x8 support an MPS of up to 2 KB. The MPAYLOAD field in
the PCI Express Device Capabilities (PCIEDCAP) register is automatically set by the hardware based on
the port’s maximum link width to reflect this.
Upstream Port Device Number
In the switch, the upstream port of a partition is assumed to have device number zero. Type 0 configura-
tion requests received by the upstream port must always target device 0 in the port. In order to meet this
requirement, Alternative Routing ID (ARI) Forwarding must be disabled in the root port or switch down-
stream port immediately above the switch partition’s upstream port.
Bus Locking
The switch supports locked transactions, allowing legacy software to run without modification on PCI
Express. Locked transactions are only supported between an upstream switch port (i.e., PCI-to-PCI bridge
function) and a downstream switch port in the same partition. Only one locked transaction sequence may
be in progress at a time.
– A locked transaction sequence is requested by the root complex by issuing a Memory Read
Request - Locked (MRdLk) transaction. A lock is established when a lock request is successfully
completed with a Completion with Data - Locked (CplDLk). A lock is released with an Unlock
message (Msg) sent by the root complex.
When the switch receives a MRdLk transaction on a partition’s upstream switch port, it forwards the
MRdLk transaction to the appropriate downstream switch port and locks the downstream switch port so that
all subsequent TLPs destined to the locked port from other ports (except the upstream port) are blocked
until the lock is released.
– Bus locking only affects TLPs that map to VC0 at the egress port. TLPs that do not map to VC0
are not affected by the lock.
2
– The MRdLK transaction obeys PCI Express ordering rules meaning that all queued posted
requests for the downstream switch port are transmitted prior to the MRdLK being transmitted.
The MRdLK is allowed by bypass queued completions.
3
– Locking of a downstream switch port does not affect transactions destined to any other port (e.g.,
transactions from the other downstream switch ports to the upstream port and peer-to-peer trans-
actions among other downstream switch ports are not blocked).
1.
Reading from a reserved address returns and undefined value. Writes to a reserved address complete success-
fully but produce undefined behavior on the register.
2.
In the PES32NT24xG2, only VC0 is supported. TLPs that don’t map to VC0 are treated as malformed. Refer to
section Error Detection and Handling by the PCI-to-PCI Bridge Function on page 10-11.
3.
Refer to section Packet Ordering on page 4-6 for further details on ordering rules.