IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 181 / 744

IDT Transparent Switch Operation
PES32NT24xG2 User Manual 10 - 11 January 30, 2013
Notes
Error Detection and Handling by the PCI-to-PCI Bridge
Function
This section describes error conditions detected by the PCI-to-PCI bridge function. This includes phys-
ical, data-link, and transaction layer errors detected by the port, as well as routing errors associated with the
PCI-to-PCI bridge function in the port.
– Internal switch errors (i.e., parity errors, switch time-out, and internal memory errors) are associ-
ated with the switch core and not with a specific port function. These errors are not described here.
Refer to section Internal Errors on page 4-16 for a detailed description of these errors.
The errors described here apply to ports that operate in a mode that includes a PCI-to-PCI bridge func-
tion (e.g., upstream switch port mode, downstream switch port mode, upstream switch port with NT function
mode, etc.) This section focuses specifically on errors related to the PCI-to-PCI bridge function
1
. Errors that
affect all functions of the port (i.e., non function-specific errors) are noted where appropriate.
Error detection and handling in the switch follows the requirements in PCI Express Base Specification.
The error checking and handling described here is performed by each PES32NT24xG2 PCI-to-PCI bridge
function. In cases where the error condition propagates among PCI-to-PCI bridge functions (e.g., a
poisoned TLP flowing from the upstream port to a downstream switch port), each PCI-to-PCI bridge func-
tion performs error checking and handling independently.
The errors described below are associated with specific actions to log and report the error. The terms
‘uncorrectable error processing’ and ‘correctable error processing’ refer to the processing described in
Section 6.2.5 of PCI Express Base Specification. Errors that are not function-specific are logged in the
corresponding status and logging registers of all functions in the port. Errors that are function-specific are
logged in the status and logging register of the affected function. Signaling of non function-specific errors
follows the rules in Section 6.2.4 of PCI Express Base Specification.
Some of the errors described below are marked as function-specific when the “function claims the TLP”.
A function claims a TLP in the following cases:
– PCI-to-PCI Bridge function
Address Routed TLPs: If received on the primary side of the bridge, the TLPs address falls
within the address space range(s) programmed in the base/limit registers. If received on the
secondary side of the bridge, always.
ID Routed TLPs: If received on the primary side of the bridge, the TLPs destination ID matches
the bus aperture range programmed in the primary/secondary/subordinate registers or matches
the bridge function’s bus/device/function assignment. If received on the secondary side of the
bridge, always.
Implicit Route TLPs: Always.
– NT Endpoint function:
Refer to section Error Detection and Handling by the NT Function on page 14-25.
– DMA function:
Refer to section PCI Express Error Handling by the DMA Function on page 15-28.
Physical Layer Errors
Table 10.7 lists error checks performed by the physical layer and the action taken when an error is
detected. Physical layer errors affect all functions of the port.
1.
Errors associated with the NT function (i.e., non-transparent operation errors) are described in Chapter 14.
Errors associated with the DMA function are described in Chapter 15.