IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 249 / 744

Notes
PES32NT24xG2 User Manual 14 - 1 January 30, 2013
®
Chapter 14
Non-Transparent Switch
Operation
Overview
The term non-transparent operation is used in this document to describe the operation of the NT func-
tion. This chapter describes the PES32NT24xG2’s non-transparent operation.
The PCI Express architectural model is one in which a root, typically the main CPU, is responsible for
configuring a tree of endpoints (i.e., a hierarchy of virtual PCI buses). Once configured, any endpoint or root
may initiate transactions. The root and endpoints share a common address space with routing configured in
PCI-PCI bridges.
A limitation of the PCI Express architectural model is that it allows only a single root and that the root
and all of the endpoints must share a common address space. This limitation may be overcome through the
use of a non-transparent bridge (NTB). A non-transparent bridge allows two or more PCI Express hierar-
chies to be interconnected with one or more shared address windows between them. The connection is
done via the NT Interconnect. Refer to section Non-Transparent Operation on page 1-8 for an introduction
to this feature.
In the PES32NT24xG2, each PCI Express hierarchy is associated with a switch partition (see Chapter 5 ,
Switch Partition and Port Configuration). Therefore, an NTB interconnects two or more switch partitions via
the NT Interconnect. When a TLP is transferred across partitions, the source partition is the partition on
which the TLP was received by the NTB, and the destination partition is the partition to which the TLP is
destined.
The PES32NT24xG2 supports eight non-transparent functions (a.k.a., NT functions or NT endpoints).
Each NT function appears as a PCI Express endpoint in the PCI Express hierarchy. The NT function is
located in a partition’s upstream port. A port configured to operate in one of the following modes contains an
NT function:
– NT function
– NT with DMA function
– Upstream switch port with NT function
– Upstream switch port with NT and DMA functions
Refer to section Switch Port Mode on page 5-5 for details on the port operating modes.
Base Address Registers (BARs)
Each NT-endpoint implements six Base Address Registers (BARs) labeled BAR 0 through BAR 5. Table
14.1 summarizes supported BAR configurations.
– All BARs may be configured to create 32-bit memory
1
windows between the PCI Express domain
and the non-transparent interconnect
2
.
– All BARs support direct address translation
– BAR 2 (or BAR 2/3 in 64-bit mode) supports direct address translation or lookup address transla-
tion
– BAR 4 (or BAR 4/5 in 64-bit mode) supports direct address translation or lookup address transla-
tion
Even and odd BARs may be paired to form 64-bit prefetchable memory space. The 4 KB configuration
space associated with the NT endpoint may be mapped into 32-bit memory using BAR 0. BAR 0 and BAR 1
may be paired to map the 4 KB configuration space associated with the NT endpoint into 64-bit memory.
See section Mapping NT Configuration Space to BAR 0 on page 14-4 for further details.
1.
The NT function’s BARs do not support I/O space.
2.
Refer to section Non-Transparent Operation on page 1-8 for a description of the non-transparent interconnect.