IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 252 / 744

IDT Non-Transparent Switch Operation
PES32NT24xG2 User Manual 14 - 4 January 30, 2013
Notes
Mapping NT Configuration Space to BAR 0
As mentioned above, the 4 KB configuration space associated with the NT endpoint may be mapped
into 32-bit memory using BAR 0. BAR 0 and BAR 1 may be paired to map the 4 KB configuration space
associated with the NT endpoint into 64-bit memory.
Mapping NT configuration space to BAR 0 allows these configuration space registers to be accessed via
memory read or writes. Mapping NT configuration space to BAR 0 requires that the MODE field be set
appropriately in the BARSETUP0 register. When NT configuration space is mapped to BAR 0, the size of
the BAR aperture is automatically set to 4 KB and the BARLIMIT0 register is ignored.
When the NT function’s configuration space is mapped to BAR 0, it is recommended that this configura-
tion space be placed in non-prefetchable memory space, as some registers may generate side-effect
actions when accessed. In addition, memory read or write requests to BAR 0 must specify a length of 1
DWord. Violating this last requirement produces undefined results.
Note: The NT function’s configuration space layout follows little-endian convention. Software
executing on a big-endian system should take this into account when accessing the NT function’s
configuration space memory-mapped to BAR 0.
TLP Translation
Direct Address Translation
All BARs may be configured to support direct address translation. Figure 14.2 illustrates the address
translation process for a BAR configured as a memory address window with direct address translation.
Figure 14.2 Direct Address Translation
The address of a TLP that falls within the effective BAR aperture of a BAR may be divided into a base
address and an offset. The base address is equal to the value programmed in BAR BADDR field bits that
are read/write. The offset address corresponds to address bits that are not part of the base address.
Associated with each BAR is a translated base address. The translated base address is a 64-bit quan-
tity. The upper 32-bits are set to zero when the translated base address is less than or equal to
0xFFFF_FFFF (i.e., lower 4 GB). The translated base address is always DWord aligned. Therefore, the
bottom two bits are always zero.
The translated address for the TLP is equal to the sum of the TLP offset address with the corresponding
translated base address field. Following formation of the translated address, the TLP header size is
adjusted accordingly:
– If the upper 32-bits of the 64-bit address are all zero, then a 3 DWord header is used.
– If the upper 32-bits of the 64-bit address are non-zero, then a 4 DWord header is used.
BAR Translated Base Address
Transaction Address
+
Translated Address
Base Address Offset