IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 139 / 744

IDT Link Operation
PES32NT24xG2 User Manual 7 - 11 January 30, 2013
Notes
When a downstream switch port’s data-link indicates a DL_Down status, the following occurs:
– All TLPs queued in the port’s ingress frame buffer (IFB) are silently discarded.
– All TLPs queued in the port’s replay buffer (EFB) are silently discarded.
– Request TLPs received by other ports and destined to the logical bus number associated with the
link that is down are treated as unsupported requests (UR) by the downstream switch port whose
link is down.
– All other TLPs received by the other ports and destined to the logical bus number associated with
the link that is down are silently discarded.
– The downstream port handles all TLPs that target the port’s function normally. It is possible to
perform configuration read and write operations to the PCI-to-PCI bridge function associated with
that downstream port.
When a link comes up, flow control credits for the configured size of the port’s IFB queues are initialized.
Following this initialization, the data-link enters the DL_Active state and reports a DL_Up condition to the
upper layers. A DL_Down condition on a downstream switch port’s link may cause the Surprise Down Error
Status (SDOENERR) bit to be set in the port’s AER Uncorrectable Error Status (AERUES) register. The
conditions under which surprise down is reported are described in Section 3.2.1 of the PCI Express Base
Specification.
Note that when a downstream port is directed by a higher layer to the hot reset state (e.g., upstream
switch port link receives training sets with the hot reset bit set, upstream switch port reports DL_Down,
upstream secondary bus reset, or downstream secondary bus reset), this is not considered a surprise down
error.
In addition to the exception conditions listed in Section 3.2.1 of the PCI Express Base Specification, the
SDOENERR bit in a port’s AERUES register is not set in the following cases:
– The partition associated with the port is placed in Disabled mode (section Partition State on page
5-3).
– The port is placed in Disabled mode (section Switch Port Mode on page 5-5).
– The port’s link is fully retrained (i.e., PHY transitions to the Detect state) as a result of a port oper-
ating mode change action (section Port Operating Mode Change on page 5-13).
– The port’s link is fully retrained via the FLRET bit in the PHYLSTATE0 register.
– The port’s clocking mode is modified (section Port Clocking Modes on page 2-2).
Slot Power Limit Support
The Set_Slot_Power_Limit message is used to convey a slot power limit value from a downstream
switch port or root port to the upstream port of a connected device or switch.
Upstream Port
When a Set_Slot_Power_Limit message is received by an upstream port, then the fields in the message
are written to the PCI Express Device Capabilities (PCIEDCAP) register of that port.
1
– Byte 0, bits 7:0 of the message payload are written to the Captured Slot Power Limit Scale
(CSPLS) field.
– Byte 1, bits 1:0 of the message payload are written to the Captured Slot Power Limit Value
(CSPLV) field.
1.
If the port is operating in a multi-function mode, the Set_Slot_Power_Limit messages targets all functions of the
port.