IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 6 / 744

IDT
PES32NT24xG2 User Manual 4 January 30, 2013
Notes
Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition
Register Terminology
Software in the context of this register terminology refers to modifications made by PCI Express root
configuration writes, writes to registers made through the slave SMBus interface, or serial EEPROM
register initialization. See Table 2.
Type Abbreviation Description
Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mechanisms
such as pin strapping or serial EEPROM. (System firmware hard-
ware initialization is only allowed for system integrated devices.)
Bits are read-only after initialization and can only be reset (for
write-once by firmware) with reset.
Read Only and Clear RC Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bit to be reset to zero.
Writing to a RC location has no effect.
Read Clear and Write RCW Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bits to be reset to zero.
Writes cause the register/bits to be modified.
Reserved Reserved The value read from a reserved register/bit is undefined. Thus,
software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined
bits and not rely on reserved bits being any particular value. On
writes, software must ensure that the values of reserved bit posi-
tions are preserved. That is, the values of reserved bit positions
must first be read, merged with the new values for other bit posi-
tions and then written back.
In addition to reserved registers, some valid register fields have
encodings marked as reserved. Such register fields must never be
written with a value corresponding to an encoding marked as
reserved. Violating this rule produces undefined operation in the
device.
Read Only RO Software can only read registers/bits with this attribute. Contents
are hardwired to a constant value or are status bits that may be
set and cleared by hardware. Writing to a RO location has no
effect.
Table 2 Register Terminology (Part 1 of 2)
0 1 2 3
bit 0 bit 31
Address of Bytes within Words: Big Endian
3 2 1 0
bit 0 bit 31
Address of Bytes within Words: Little Endian