IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 590 / 744

IDT DMA Function Registers
PES32NT24xG2 User Manual 23 - 2 January 30, 2013
Notes
2 BME RW 0x0 Bus Master Enable.
When this bit is set, the DMA function is allowed to issue
memory requests. When this bit is cleared, the DMA func-
tion does not transmit memory requests.
Note that the DMA function never issues I/O requests.
Also, note that clearing this bit inhibits the DMA function
from issuing MSI requests.
Completions or messages generated by the function (i.e., a
completion corresponding to a configuration request) are
not affected by this bit.
0x0 - (disable) Disable transmission of memory requests.
0x1 - (enable) Enable transmission of memory requests.
3 SSE RO 0x0 Special Cycle Enable.
Not applicable.
4 MWI RO 0x0 Memory Write Invalidate.
Not applicable.
5 VGAS RO 0x0 VGA Palette Snoop.
Not applicable.
6 PERRE RW 0x0 Parity Error Enable.
This bit controls the logging of poisoned TLPs in the Master
Data Parity Error Detected (MDPED) field in the PCI Status
(PCISTS) register. When this bit is cleared, poisoned TLPs
are not reported as master data parity errors in the PCISTS
register.
7 ADSTEP RO 0x0 Address Data Stepping.
Not applicable.
8 SERRE RW 0x0 SERR Enable.
Non-fatal and fatal errors detected by the function are
reported to the Root Complex when this bit is set or the bits
in the PCI Express Device Control register are set.
0x0 - (disable) Disable non-fatal and fatal error reporting if
also disabled in Device Control register.
0x1 - (enable) Enable non-fatal and fatal error reporting.
9 FB2B RO 0x0 Fast Back-to-Back Enable.
Not applicable.
10 INTXD RW 0x0 INTx Disable.
Controls the ability of the function to generate an INTx inter-
rupt message.
When this bit is set, INTx interrupts generated by this func-
tion are negated. This may result in a change in the
resolved interrupt state of the function.
15:11 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description