IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 418 / 744

IDT PCI-to-PCI Bridge Registers
PES32NT24xG2 User Manual 20 - 34 January 30, 2013
Notes
6 SDE RWL 0x0
SWSticky
Selectable De-emphasis.
For a downstream switch port, this bit sets the de-emphasis
level when the link operates at 5.0 GT/s.
Per the PCI Express Base Specification, this bit is not appli-
cable for upstream ports. Still, for the switch’s upstream
port, this bit selects the de-emphasis preference advertised
via training sets (the actual de-emphasis on the link is
selected by the link partner).
0x0 - De-emphasis level = -6.0 dB
0x1 - De-emphasis level = -3.5 dB
This bit has no effect when the link operates at 2.5 GT/s, or
when the link operates in low-swing mode.
When this field is modified, the newly selected de-emphasis
is not applied until the PHY LTSSM transitions through the
states in which it is allowed to modify the de-emphasis set-
ting on the line (e.g., Recovery.Speed). Therefore, after
modifying this field, it is recommended that the link be fully
retrained by setting the FLRET bit in the PHYLSTATE0 reg-
ister.
9:7 TM RW 0x0
Sticky
Transmit Margin.
This field controls the value of the non de-emphasized volt-
age level at the transmitter pins. This field is reset to 0x0 on
entry to the LTSSM Polling.Configuration substate.
0x0 - Normal operating range
0x1 - 900 mV for full swing and 500 mV for low-swing
0x2 - 700 mV for full swing and 400 mV for low-swing
0x3 - 500 mV for full swing and 300 mV for low-swing
0x4 - 300 mV for full swing and 200 mv for low-swing
0x5 - 200 mV for full swing and 100 mv for low-swing
0x6 - 0x7 - Reserved
This register is intended for debug and compliance testing
purposes only. System firmware and software is allowed to
modify this register only during debug or compliance test-
ing. In all other cases, the system must ensure that this reg-
ister is set to the default value.
When this field is set to “Normal Operating Range”, the
SerDes transmitter drive level is selected via the SerDes
Transmitter Control registers (S[x]TXLCTL0 and
S[x]TXLCTL1). Refer to section SerDes Transmitter Con-
trols on page 8-3.
When this field is modified, the newly selected value is not
applied until the PHY LTSSM transitions through the states
in which it is allowed to modify the transmit margin setting
on the line (i.e., Recovery.RcvrLock). Therefore, after modi-
fying this field, it is recommended that the link be retrained
by setting the LRET bit in the PCIELCTL register.
Note: This field has no effect when the port operates in
SerDes Test mode.
Bit
Field
Field
Name
Type Default
Value
Description