IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 303 / 744

IDT DMA Controller
PES32NT24xG2 User Manual 15 - 15 January 30, 2013
Notes
• If the address is below 4 GB, then a MWr TLP with a 32-bit address is generated. If the address
is above 4 GB, then a MWr TLP with a 64-bit address is generated.
– The Byte Count (BCOUNT) field specifies the number of bytes to transfer.
• Transferred bytes are written contiguously to the locations starting at the destination address.
• Setting this field to a reserved value results in no data being transferred.
– The Data Lower field contains the first 4 bytes of data to be transferred.
• DATAL[7:0] corresponds to the first byte, DATAL[15:8] corresponds to the second byte, and so
on.
– The Data Upper field contains the next 4 bytes of data to be transferred.
• DATAL[7:0] corresponds to the fifth byte, DATAL[15:8] corresponds to the sixth byte, and so on.
• The Data Upper field is valid when the Byte Count indicates that 5 or more bytes. Otherwise, the
data in this field is not transferred.
– Immediate data transfers do not support constant addressing. Data bytes are written contiguously
to the target location(s), starting at the specified destination address.
• In PCI Express, requests must not specify an address/length combination that causes a memory
space access to cross a 4-KB boundary. The DMA controller may generate multiple memory
write TLPs if the transfer were to otherwise cross a 4-KB boundary.
DMA Descriptor Processing
DMA descriptor processing consists of reading a descriptor from memory, executing the operation
outlined by the descriptor, writing back updated descriptor completion status and then proceeding to the
next descriptor.
Descriptor List Processing
DMA descriptor processing is initiated as a result of the following events when the Error (E) bit in the
DMAxSTS register is cleared.
– Setting of the Run (RUN) bit in the DMA Channel Control (DMACxCTL) register when the DMA
channel is idle.
– As a side effect of writing a non-zero value to the DMA Channel Descriptor Pointer Low (DMACx-
DPTRL) register.
• Initiation of a DMA descriptor processing as a side effect of writing to the DMACxDPTRL register
may be disabled by setting the Disable DMACxDPTRL Descriptor Processing Initiation
(DISADPTRL) bit in the DMA Channel Configuration (DMAxCFG) register.
– As a side effect of writing a non-zero value to the DMA Channel Descriptor Pointer High (DMACx-
DPTRH) register.
• Initiation of a DMA descriptor processing as a side effect of writing to the DMACxDPTRH
register may be disabled by setting the Disable DMACxDPTRH Descriptor Processing Initiation
(DISADPTRH) bit in the DMA Channel Configuration (DMAxCFG) register.
– As a side effect of writing a non-zero value to the DMA Channel Next Descriptor Pointer Low
(DMACxNDPTRL) or DMA Channel Next Descriptor Pointer High (DMACxNDPTRH) registers, as
explained in section Descriptor Chaining on page 15-16.
The DMACxDPTRL and DMACxDPTRH registers together form a 64-bit descriptor address. When DMA
descriptor processing is initiated, the DMA controller reads and begins processing the descriptor at the
address pointed to by the 64-bit descriptor address.
– When DMA descriptor processing is initiated, the RUN bit in the DMAxCTL register is set.
When the DMA channel finishes processing of a descriptor, updated descriptor status is written back to
memory. When writing back the updated descriptor status, the DMA uses PCI Express byte enables to only
update the fourth byte in the first DWord of the descriptor (i.e., the memory byte where the DSTS field is
located).
If the next descriptor address is non-zero (i.e., NEXTL/H are non-zero), then the DMA channel proceeds
to process the descriptor located at that address. If the next descriptor address is zero or if the LST bit in
the descriptor is set to 0x1, and chaining is not enabled as described in section Descriptor Chaining on
page 15-16, then the DMA channel halts descriptor processing.