IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 347 / 744

IDT Register Organization
PES32NT24xG2 User Manual 19 - 3 January 30, 2013
Notes
registers associated with the NT function of a port (refer to section NT Function Registers on page 19-14).
DMA endpoint registers correspond to the configuration registers associated with the DMA function of a
port (refer to section DMA Function Registers on page 19-23).
The switch configuration and status register region contains registers that control general operation of
the switch and are proprietary in nature (e.g., registers to configure the switch ports and partitions, etc.).
The offset address for switch configuration and status registers is defined in section Switch Configuration
and Status Registers on page 19-29.
The entire device’s global address space may be accessed using PCI Express configuration requests
from any the device’s PCI Express function (e.g., PCI-to-PCI bridge function, NT function, DMA function,
etc.).
– Located in each function is a Global Address Space Access Address (GASAADDR) register and
a Global Address Space Access Data (GASADATA) register.
– The DWord system address of the register to be accessed is written to the Address (ADDR) field
in the GASAADDR register. When a read is performed to the Data (DATA) field in the GASADATA
register, the value of the corresponding register selected by the ADDR field is returned. When a
write is performed to the DATA field, the value of the corresponding register selected by the ADDR
field is updated with the value written.
– Any software visible register in the entire PES32NT24xG2 switch may be accessed using a func-
tion’s GASAADDR and GASADATA registers, even those associated with functions in other ports
and partitions. In some applications it is desirable to restrict access to these registers.
• Associated with each port is a bit in the Port (PORT) field of the Global Address Space Access
Protection (GASAPROT) register. When a bit in this field is set, access to the global address
space using the GASAADDR and GASADATA registers from the corresponding port is disabled
and all fields in these registers become read only with a value of zero.
– Access to the global address space registers may be done via PCI Express configuration
accesses, via the SMBus slave interface, or via serial EEPROM.
• SMBus or serial EEPROM accesses are not affected by the global address space protection
register.
Partial-Byte Access to Word and DWord Registers
Configuration registers in the switch have different sizes (e.g., Byte, Word, DWord). Registers should be
accessed with byte-enables that correspond to their native size or a size of one DWord. For example, a
Byte register should be read or written with only one byte enable set, or with all four byte enables set. A
DWord register should be read or written with all the byte-enables set.
Configuration Register Side-Effects
There are software visible configuration registers that have a side-effect action when written and this
side-effect action may affect the ability of the switch to respond with a completion. A configuration write to
such a register always returns a completion to the link partner before the side-effect action is performed.
This is implemented by delaying the side-effect action by 1ms following generation of the completion. If
the completion is not accepted by the link partner in this time interval, then the completion will be lost.
The following registers, when written
1
, have a side-effect action delay.
– PCI-to-PCI Bridge function registers
• PHYLSTATE0.FLRET
– Switch Configuration and Status Registers
• SWPORTxCTL.MODE
1.
The side-effect delay is applied by the hardware when the registers listed are written via PCI Express configura-
tion requests, as well as EEPROM or SMBus accesses.