IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 736 / 744

IDT Usage Models
PES32NT24xG2 User Manual 26 - 26 January 30, 2013
Notes
Figure 26.15 Active/Active System Configuration Before Failover Event
If at a later timer the failed root is repaired or replaced, a partition fundamental reset in the partition
connected to the failed root complex is expected. The platform is responsible for asserting this fundamental
reset to the switch (via the partition fundamental reset pin associated with the appropriate GPIO alternate
function pin).
The switch’s event signaling mechanism notifies the partition fundamental reset event to partitions 0 and
1. The notification results in an interrupt being generated by the upstream port in the partition associated
with the root which did not fail. Continuing with the previous example, if RC0 had failed and is later
replaced, the platform asserts the fundamental reset associated with partition 0 (i.e., via GPIO[0]). As a
result, the switch’s event signaling mechanism detects a partition fundamental reset event in partition 0.
The switch’s event signaling mechanism notifies this event to partitions 0 and 1. This in turn causes the
PCI-to-PCI bridge function in port 8 to generate and send an interrupt to RC1. Note that since partition 0 is
empty (i.e., port 0 is unattached and ports 4 and 6 are in partition 1 as a result of the failover), no further
action occurs in this partition.
Upon receiving the interrupt, the root checks the source of this interrupt by inspecting the PCI-to-PCI
bridge Interrupt Status (P2PINTSTS), Switch Event status (SESTS), and Switch Event Link Up Status
(SELINKUPSTS) registers. In this way, the root determines that the interrupt is due to a partition funda-
mental reset in a partition associated with another root complex. The root complex clears the event status
bits during the inspection to re-arm the event signaling mechanism.
Continuing with the previous example, after RC1 receives the interrupt, it inspects the P2PINTSTS,
SESTS, and SELINKUPSTS registers and determines that partition 0 has experiences a fundamental reset.
RC1 clears the bits in the SELINKUPSTS and P2PINTSTS registers to re-arm the event signaling mecha-
nism.
In order to restore the system to its initial configuration (shown in Figure 26.14 above), the root complex
that received the interrupt proceeds to de-allocate any system resources associated with the ports that it
will migrate out of the partition, and then reconfigures the switch by programming the SWPORTxCTL regis-
ters corresponding to the ports that will be migrated.
Continuing with the previous example, RC1 de-allocates system resources associated with ports 4 and
6, and then it resets and migrates these ports to partition 0. In addition, RC1 resets and modifies the oper-
ating mode of port 0 to upstream switch port with NT function mode, placing it in partition 0. To ensure
RC1
EP12 EP16
Partition 1
P2P
P12
(P2P)
P16
(P2P)
RC0
EP4 EP6
Partition 0
( Active)
P 0
(UN)
P4
(P2P)
P6
(P2P)
Serial
EEPROM
Switch
NT
Port 8
PART1 PERSTN PART0 PERSTN