IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 310 / 744

IDT DMA Controller
PES32NT24xG2 User Manual 15 - 22 January 30, 2013
Notes
Descriptor Prefetching
When the amount of data moved by data transfer descriptors is small (e.g., when moving data associ-
ated with 64B packets), the overhead in fetching DMA descriptors from memory between data transfer
operations may limit performance.
To overcome this overhead, the DMA channel supports descriptor prefetching. When descriptor
prefetching is enabled, the DMA channel issues memory read requests for DMA descriptors before they are
required. This allows the memory latency associated with fetching descriptors to be overlapped with data
transfer operations.
– When descriptor prefetching is enabled, the DMA controller follows the NEXTL/NEXTH field and
issues memory read requests for descriptors before they are required (i.e., before the descriptor
processing associated with a previous descriptor has completed).
– The DMA channel queues prefetched descriptors until they are processed. Prefetched descriptors
are discarded when DMA channel operation is suspended or aborted.
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– Descriptor prefetching stops when the end of a descriptor list is reached. Descriptor prefetching
does not initiate descriptor chaining.
By default, descriptor prefetching is disabled in the DMA. Descriptor prefetching may be enabled
through the DMA Descriptor Prefetch Level (DPREFETCH) field in the DMA Channel Configuration
(DMACxCFG) register.
DMA Request Rate Control
By default, a DMA channel issues data transfer memory read requests when needed. While this
provides the highest level of performance, it can also lead to congestion in the PCI Express topology and
tax memory bandwidth.
To support background DMA operations (i.e., ones that consume only a fraction of available system
bandwidth), each DMA channel supports a request rate control capability. Request rate control is enabled
and controlled by the value in the Request Rate (RR) field of the DMA Channel Request Rate Control
(DMACxRRCTL) register.
When request rate control is enabled, a counter is loaded when each data transfer memory read request
(MRd) TLP is issued with the number of DWords requested by that TLP. While non-zero, the counter is
decremented by the rate indicated by the RR field. For example, a value of one in the RR field indicates that
the counter is decremented every 4 ns while a value of 1000 in the RR field indicates that the counter is
decremented every 4 us. A new memory transfer read request is not issued until the counter is zero.
– Assuming no other overhead, the bandwidth consumed by data transfers is equal to approxi-
mately (1000 * DWords)/RR MBps.
– A RR value of 1000 results in the DMA channel consuming approximately 1 MBps of memory read
and memory write bandwidth.
Request rate control has no effect on descriptor memory read requests and data transfer memory write
requests.
– Since completions associated with memory read requests are transformed into memory write
requests, the request rate controls both the completion bandwidth as well as the memory write
request bandwidth.
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This includes descriptors in the process of being prefetched. In this case, the DMA waits for the prefetching to
complete and then discards the descriptor.