IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 66 / 744

IDT Reset and Initialization
PES32NT24xG2 User Manual 3 - 2 January 30, 2013
Notes
Switch Fundamental Reset
A switch fundamental reset may be cold or warm. A cold switch fundamental reset occurs following a
device being powered-on and assertion of the global reset (PERSTN) signal. A warm switch fundamental
reset occurs when a switch fundamental reset is initiated while power remains applied. The
PES32NT24xG2 behaves in the same manner regardless of whether the switch fundamental reset is cold
or warm.
A switch fundamental reset may be initiated by any of the following conditions.
– A cold switch fundamental reset initiated by application of power (i.e., a power-on) followed by
assertion of the global reset (PERSTN) signal.
Note: Refer to the device data-sheet for power sequencing requirements.
– A warm switch fundamental reset initiated by assertion of PERSTN while power remains applied.
When a switch fundamental reset is initiated, the following sequence is executed.
1. Wait for the switch fundamental reset condition to clear (e.g., negation of PERSTN).
2. On negation of PERSTN, sample the boot configuration vector signals shown in Table 3.2.
3. All registers are initialized to their default value.
– Partition and port configuration registers are initialized as dictated by the SWMODE value in the
boot configuration vector (see section Switch Modes on page 3-10).
4. The Register Unlock (REGUNLOCK) bit is set in the Switch Control (SWCTL) register. This allows
all register fields with type Read-Write-Locked (RWL) to be modified.
5. The on-chip PLL and SerDes are initialized (e.g., PLL lock).
6. The master SMBus interface is initialized.
7. The slave SMBus is taken out of reset and initialized. The slave SMBus address is specified by the
SSMBADDR[2:1] signals in the boot configuration vector.
8. Within 20 ms after the switch fundamental reset condition clears, the reset signal to the stacks is
negated and link training begins on all ports. While link training takes place, execution of the reset
sequence continues.
9. Within 100 ms following clearing of the switch fundamental reset condition, the following occurs.
– All ports that have PCI Express base specification compliant link partners have completed link
training.
– All ports are able to receive and process TLPs.
10. If the sampled Switch Mode (SWMODE) state corresponds to a mode that supports serial EEPROM
initialization, then the contents of the serial EEPROM are read and appropriate switch registers are
updated. Otherwise, this step is not executed.
– Refer to section Serial EEPROM on page 12-2 for details on serial EEPROM initialization.
– While the contents of the EEPROM are read, all ports enter a quasi-reset state. In quasi-reset
state, each port responds to all type 0 configuration request TLPs with a configuration-request-
retry-status completion
1
. All other TLPs are ignored (i.e., flow control credits are returned but the
TLP is discarded).
– If a one is written by the serial EEPROM to the Full Link Retrain (FLRET) bit in any Phy Link State
0 (PHYLSTATE0) register, then link retraining is initiated on the corresponding port using the
current link parameters.
– If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM
is aborted and the RSTHALT bit is set in the SWCTL register. Error information is recorded in the
SMBUSSTS register (refer to section Initialization from Serial EEPROM on page 12-3).
1.
This includes configuration requests to the port’s Global Address Space Access and Data registers
(GASAADDR and GASADATA). Type 1 configuration request TLPs are handled as unsupported requests.