IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 75 / 744

IDT Reset and Initialization
PES32NT24xG2 User Manual 3 - 11 January 30, 2013
Notes
Single Partition Mode
In single partition mode, the initial values outlined in Table 3.9 result in the following configuration.
– All ports are members of partition zero.
– Port 0 is configured as the upstream switch port of partition zero. All other ports are configured as
downstream switch ports of partition zero.
– The initial state of partition zero is active. The initial state of all other partitions is disabled.
Multi-Partition with Unattached Ports
In this mode, the initial values outlined in Table 3.9 result in the following configuration.
– All ports are configured to operate in unattached mode.
– The initial state of all partitions is disabled.
Multi-Partition with Disabled Ports
In this mode, the initial values outlined in Table 3.9 result in the following configuration.
– All ports are configured to operate in disabled mode.
The initial state of all partitions is disabled.
Partition Resets
A partition reset is a reset that is associated with a specific switch partition. The reset has an effect only
on those functions and ports associated with that switch partition. It has no effect on the operation of other
switch partitions, ports in other switch partitions, or logic not associated with a switch partition (e.g., master
SMBus, slave SMBus).
A partition reset may be subdivided into four subcategories: partition fundamental reset, partition hot
reset, partition upstream secondary bus reset, and partition downstream secondary bus reset. These
subcategories correspond to resets defined by the PCI architecture.
– A partition fundamental reset logically causes all logic associated with a partition to take on its
initial state, but does not cause the state of register fields denoted as SWSticky to be modified.
– A partition hot reset logically causes all logic in the partition to be returned to an initial state, but
does not cause the state of register fields denoted as Sticky or SWSticky to be modified.
– A partition upstream secondary bus reset is only applicable to partitions with an upstream switch
port
1
. This type of reset logically causes all devices on the virtual PCI bus of a partition to be hot
reset except the upstream port.
Register and Field
Switch Mode (SWMODE)
Single Partition
(0x0 to 0x3, 0x8
and 0x9)
Multi-Partition
with Unattached
Ports
(0xA, 0xB, 0xC
or 0xD)
Multi-Partition
with Disabled
Ports
(0xE or 0xF)
SWPART[0]CTL.STATE 0x1 0x0 0x0
SWPART[7:1]CTL.STATE 0x0 0x0 0x0
SWPORT[0]CTL.MODE 0x2 0x5 0x0
SWPORT[23:1]CTL.MODE 0x1 0x5 0x0
Table 3.9 Switch Mode Dependent Register Initialization
1.
Refer to section Switch Partitions on page 5-1 for a description of the port operating modes that are considered
upstream switch ports, etc.